#!/ciena/bin/regdecode64 0x00011800B0000000

[PCS0_MR0_CONTROL_REG]
offset: 0x1000

[PCS0_MR0_STATUS_REG]
offset: 0x1008

[PCS0_AN0_ADV_REG]
offset: 0x1010

[PCS0_AN0_LP_ABIL_REG]
offset: 0x1018

[PCS0_AN0_RESULTS_REG]
offset: 0x1020

[PCS0_AN0_EXT_ST_REG]
offset: 0x1028

[PCS0_LINK0_TIMER_COUNT_REG]
offset: 0x1040

[PCS0_TX_RX0_POLARITY_REG]
offset: 0x1048

[PCS0_RX0_SYNC_REG]
offset: 0x1050

[PCS0_RX0_STATES_REG]
offset: 0x1058

[PCS0_TX0_STATES_REG]
offset: 0x1060

[PCS0_SGM0_AN_ADV_REG]
offset: 0x1068

[PCS0_SGM0_LP_ADV_REG]
offset: 0x1070

[PCS0_MISC0_CTL_REG]
offset: 0x1078

[PCS0_INT0_REG]
offset: 0x1080

[PCS0_INT0_EN_REG]
offset: 0x1088

[PCS0_LOG_ANL0_REG]
offset: 0x1090

[PCS0_MR1_CONTROL_REG]
offset: 0x1400

[PCS0_MR1_STATUS_REG]
offset: 0x1408

[PCS0_AN1_ADV_REG]
offset: 0x1410

[PCS0_AN1_LP_ABIL_REG]
offset: 0x1418

[PCS0_AN1_RESULTS_REG]
offset: 0x1420

[PCS0_AN1_EXT_ST_REG]
offset: 0x1428

[PCS0_LINK1_TIMER_COUNT_REG]
offset: 0x1440

[PCS0_TX_RX1_POLARITY_REG]
offset: 0x1448

[PCS0_RX1_SYNC_REG]
offset: 0x1450

[PCS0_RX1_STATES_REG]
offset: 0x1458

[PCS0_TX1_STATES_REG]
offset: 0x1460

[PCS0_SGM1_AN_ADV_REG]
offset: 0x1468

[PCS0_SGM1_LP_ADV_REG]
offset: 0x1470

[PCS0_MISC1_CTL_REG]
offset: 0x1478

[PCS0_INT1_REG]
offset: 0x1480

[PCS0_INT1_EN_REG]
offset: 0x1488

[PCS0_LOG_ANL1_REG]
offset: 0x1490

[PCS0_MR2_CONTROL_REG]
offset: 0x1800

[PCS0_MR2_STATUS_REG]
offset: 0x1808

[PCS0_AN2_ADV_REG]
offset: 0x1810

[PCS0_AN2_LP_ABIL_REG]
offset: 0x1818

[PCS0_AN2_RESULTS_REG]
offset: 0x1820

[PCS0_AN2_EXT_ST_REG]
offset: 0x1828

[PCS0_LINK2_TIMER_COUNT_REG]
offset: 0x1840

[PCS0_TX_RX2_POLARITY_REG]
offset: 0x1848

[PCS0_RX2_SYNC_REG]
offset: 0x1850

[PCS0_RX2_STATES_REG]
offset: 0x1858

[PCS0_TX2_STATES_REG]
offset: 0x1860

[PCS0_SGM2_AN_ADV_REG]
offset: 0x1868

[PCS0_SGM2_LP_ADV_REG]
offset: 0x1870

[PCS0_MISC2_CTL_REG]
offset: 0x1878

[PCS0_INT2_REG]
offset: 0x1880

[PCS0_INT2_EN_REG]
offset: 0x1888

[PCS0_LOG_ANL2_REG]
offset: 0x1890

[PCS0_MR3_CONTROL_REG]
offset: 0x1C00

[PCS0_MR3_STATUS_REG]
offset: 0x1C08

[PCS0_AN3_ADV_REG]
offset: 0x1C10

[PCS0_AN3_LP_ABIL_REG]
offset: 0x1C18

[PCS0_AN3_RESULTS_REG]
offset: 0x1C20

[PCS0_AN3_EXT_ST_REG]
offset: 0x1C28

[PCS0_LINK3_TIMER_COUNT_REG]
offset: 0x1C40

[PCS0_TX_RX3_POLARITY_REG]
offset: 0x1C48

[PCS0_RX3_SYNC_REG]
offset: 0x1C50

[PCS0_RX3_STATES_REG]
offset: 0x1C58

[PCS0_TX3_STATES_REG]
offset: 0x1C60

[PCS0_SGM3_AN_ADV_REG]
offset: 0x1C68

[PCS0_SGM3_LP_ADV_REG]
offset: 0x1C70

[PCS0_MISC3_CTL_REG]
offset: 0x1C78

[PCS0_INT3_REG]
offset: 0x1C80

[PCS0_INT3_EN_REG]
offset: 0x1C88

[PCS0_LOG_ANL3_REG]
offset: 0x1C90

