#!/ciena/bin/regdecode64 0x0001180000000000

[CN3120_MIO_BOOT_REG_CFG0]
name:
width: 64
field:	63:37	—	Reserved
field:	36	SAM	strobe and mode
field:	35:34	WE_EXT	write-enable count extension
field:	33:32	OE_EXT	output-enable count extension
field:	31	EN	enable
field:	30	OR	Reserved (since there is no previous region)
field:	29	ALE	address-latch enable
value:		0	non-multiplexed	address/data bus
value:		1	multiplexed	address/data bus
field:	28	WIDTH	data-bus width
value:		0	_8_bit
value:		1	_16_bit
field:	27:16	SIZE	Region size is specified in 64K blocks in “block−1” i.e. 0 = 1 64K block
field:	15:0	BASE	base address specifies address bits [31:16] of the first 64K block of the region

[CN3120_MIO_BOOT_REG_CFG1]
field:	63:37	—	Reserved
field:	36	SAM	strobe and mode
field:	35:34	WE_EXT	write-enable count extension
field:	33:32	OE_EXT	output-enable count extension
field:	31	EN	enable
field:	30	OR	Asserts the given region’s chip enable when there is an address hit in the previous region
field:	29	ALE	address-latch enable
value:		0	non-multiplexed	address/data bus
value:		1	multiplexed	address/data bus
field:	28	WIDTH	data-bus width
value:		0	_8_bit
value:		1	_16_bit
field:	27:16	SIZE	Region size is specified in 64K blocks in “block−1” i.e. 0 = 1 64K block
field:	15:0	BASE	base address specifies address bits [31:16] of the first 64K block of the region

[CN3120_MIO_BOOT_REG_CFG2]
field:	63:37	—	Reserved
field:	36	SAM	strobe and mode
field:	35:34	WE_EXT	write-enable count extension
field:	33:32	OE_EXT	output-enable count extension
field:	31	EN	enable
field:	30	OR	Asserts the given region’s chip enable when there is an address hit in the previous region
field:	29	ALE	address-latch enable
value:		0	non-multiplexed	address/data bus
value:		1	multiplexed	address/data bus
field:	28	WIDTH	data-bus width
value:		0	_8_bit
value:		1	_16_bit
field:	27:16	SIZE	Region size is specified in 64K blocks in “block−1” i.e. 0 = 1 64K block
field:	15:0	BASE	base address specifies address bits [31:16] of the first 64K block of the region

[CN3120_MIO_BOOT_REG_CFG3]
field:	63:37	—	Reserved
field:	36	SAM	strobe and mode
field:	35:34	WE_EXT	write-enable count extension
field:	33:32	OE_EXT	output-enable count extension
field:	31	EN	enable
field:	30	OR	Asserts the given region’s chip enable when there is an address hit in the previous region
field:	29	ALE	address-latch enable
value:		0	non-multiplexed	address/data bus
value:		1	multiplexed	address/data bus
field:	28	WIDTH	data-bus width
value:		0	_8_bit
value:		1	_16_bit
field:	27:16	SIZE	Region size is specified in 64K blocks in “block−1” i.e. 0 = 1 64K block
field:	15:0	BASE	base address specifies address bits [31:16] of the first 64K block of the region

[CN3120_MIO_BOOT_REG_CFG4]
field:	63:37	—	Reserved
field:	36	SAM	strobe and mode
field:	35:34	WE_EXT	write-enable count extension
field:	33:32	OE_EXT	output-enable count extension
field:	31	EN	enable
field:	30	OR	Asserts the given region’s chip enable when there is an address hit in the previous region
field:	29	ALE	address-latch enable
value:		0	non-multiplexed	address/data bus
value:		1	multiplexed	address/data bus
field:	28	WIDTH	data-bus width
value:		0	_8_bit
value:		1	_16_bit
field:	27:16	SIZE	Region size is specified in 64K blocks in “block−1” i.e. 0 = 1 64K block
field:	15:0	BASE	base address specifies address bits [31:16] of the first 64K block of the region

[CN3120_MIO_BOOT_REG_CFG5]
field:	63:37	—	Reserved
field:	36	SAM	strobe and mode
field:	35:34	WE_EXT	write-enable count extension
field:	33:32	OE_EXT	output-enable count extension
field:	31	EN	enable
field:	30	OR	Asserts the given region’s chip enable when there is an address hit in the previous region
field:	29	ALE	address-latch enable
value:		0	non-multiplexed	address/data bus
value:		1	multiplexed	address/data bus
field:	28	WIDTH	data-bus width
value:		0	_8_bit
value:		1	_16_bit
field:	27:16	SIZE	Region size is specified in 64K blocks in “block−1” i.e. 0 = 1 64K block
field:	15:0	BASE	base address specifies address bits [31:16] of the first 64K block of the region

[CN3120_MIO_BOOT_REG_CFG6]
field:	63:37	—	Reserved
field:	36	SAM	strobe and mode
field:	35:34	WE_EXT	write-enable count extension
field:	33:32	OE_EXT	output-enable count extension
field:	31	EN	enable
field:	30	OR	Asserts the given region’s chip enable when there is an address hit in the previous region
field:	29	ALE	address-latch enable
value:		0	non-multiplexed	address/data bus
value:		1	multiplexed	address/data bus
field:	28	WIDTH	data-bus width
value:		0	_8_bit
value:		1	_16_bit
field:	27:16	SIZE	Region size is specified in 64K blocks in “block−1” i.e. 0 = 1 64K block
field:	15:0	BASE	base address specifies address bits [31:16] of the first 64K block of the region

[CN3120_MIO_BOOT_REG_CFG7]
field:	63:37	—	Reserved
field:	36	SAM	strobe and mode
field:	35:34	WE_EXT	write-enable count extension
field:	33:32	OE_EXT	output-enable count extension
field:	31	EN	enable
field:	30	OR	Asserts the given region’s chip enable when there is an address hit in the previous region
field:	29	ALE	address-latch enable
value:		0	non-multiplexed	address/data bus
value:		1	multiplexed	address/data bus
field:	28	WIDTH	data-bus width
value:		0	_8_bit
value:		1	_16_bit
field:	27:16	SIZE	Region size is specified in 64K blocks in “block−1” i.e. 0 = 1 64K block
field:	15:0	BASE	base address specifies address bits [31:16] of the first 64K block of the region


[CN3120_MIO_BOOT_REG_TIM0]
field:	63	PAGEM	page-mode enable
field:	62	WAITM	wait-mode enable
field:	61:60	PAGES	page size
field:	59:54	ALE	ALE count
field:	53:48	PAGE	page count
field:	47:42	WAIT	wait count, must be nonzero when WAITM is set to 1
field:	41:36	PAUSE	pause count
field:	35:30	WR_HLD	write hold count
field:	29:24	RD_HLD	read hold count
field:	23:18	WE	write enable count
field:	17:12	OE	output enable count
field:	11:6	CE	chip enable count
field:	5:0	ADR	address count

[CN3120_MIO_BOOT_REG_TIM1]
field:	63	PAGEM	page-mode enable
field:	62	WAITM	wait-mode enable
field:	61:60	PAGES	page size
field:	59:54	ALE	ALE count
field:	53:48	PAGE	page count
field:	47:42	WAIT	wait count, must be nonzero when WAITM is set to 1
field:	41:36	PAUSE	pause count
field:	35:30	WR_HLD	write hold count
field:	29:24	RD_HLD	read hold count
field:	23:18	WE	write enable count
field:	17:12	OE	output enable count
field:	11:6	CE	chip enable count
field:	5:0	ADR	address count

[CN3120_MIO_BOOT_REG_TIM2]
field:	63	PAGEM	page-mode enable
field:	62	WAITM	wait-mode enable
field:	61:60	PAGES	page size
field:	59:54	ALE	ALE count
field:	53:48	PAGE	page count
field:	47:42	WAIT	wait count, must be nonzero when WAITM is set to 1
field:	41:36	PAUSE	pause count
field:	35:30	WR_HLD	write hold count
field:	29:24	RD_HLD	read hold count
field:	23:18	WE	write enable count
field:	17:12	OE	output enable count
field:	11:6	CE	chip enable count
field:	5:0	ADR	address count

[CN3120_MIO_BOOT_REG_TIM3]
field:	63	PAGEM	page-mode enable
field:	62	WAITM	wait-mode enable
field:	61:60	PAGES	page size
field:	59:54	ALE	ALE count
field:	53:48	PAGE	page count
field:	47:42	WAIT	wait count, must be nonzero when WAITM is set to 1
field:	41:36	PAUSE	pause count
field:	35:30	WR_HLD	write hold count
field:	29:24	RD_HLD	read hold count
field:	23:18	WE	write enable count
field:	17:12	OE	output enable count
field:	11:6	CE	chip enable count
field:	5:0	ADR	address count

[CN3120_MIO_BOOT_REG_TIM4]
field:	63	PAGEM	page-mode enable
field:	62	WAITM	wait-mode enable
field:	61:60	PAGES	page size
field:	59:54	ALE	ALE count
field:	53:48	PAGE	page count
field:	47:42	WAIT	wait count, must be nonzero when WAITM is set to 1
field:	41:36	PAUSE	pause count
field:	35:30	WR_HLD	write hold count
field:	29:24	RD_HLD	read hold count
field:	23:18	WE	write enable count
field:	17:12	OE	output enable count
field:	11:6	CE	chip enable count
field:	5:0	ADR	address count

[CN3120_MIO_BOOT_REG_TIM5]
field:	63	PAGEM	page-mode enable
field:	62	WAITM	wait-mode enable
field:	61:60	PAGES	page size
field:	59:54	ALE	ALE count
field:	53:48	PAGE	page count
field:	47:42	WAIT	wait count, must be nonzero when WAITM is set to 1
field:	41:36	PAUSE	pause count
field:	35:30	WR_HLD	write hold count
field:	29:24	RD_HLD	read hold count
field:	23:18	WE	write enable count
field:	17:12	OE	output enable count
field:	11:6	CE	chip enable count
field:	5:0	ADR	address count

[CN3120_MIO_BOOT_REG_TIM6]
field:	63	PAGEM	page-mode enable
field:	62	WAITM	wait-mode enable
field:	61:60	PAGES	page size
field:	59:54	ALE	ALE count
field:	53:48	PAGE	page count
field:	47:42	WAIT	wait count, must be nonzero when WAITM is set to 1
field:	41:36	PAUSE	pause count
field:	35:30	WR_HLD	write hold count
field:	29:24	RD_HLD	read hold count
field:	23:18	WE	write enable count
field:	17:12	OE	output enable count
field:	11:6	CE	chip enable count
field:	5:0	ADR	address count

[CN3120_MIO_BOOT_REG_TIM7]
field:	63	PAGEM	page-mode enable
field:	62	WAITM	wait-mode enable
field:	61:60	PAGES	page size
field:	59:54	ALE	ALE count
field:	53:48	PAGE	page count
field:	47:42	WAIT	wait count, must be nonzero when WAITM is set to 1
field:	41:36	PAUSE	pause count
field:	35:30	WR_HLD	write hold count
field:	29:24	RD_HLD	read hold count
field:	23:18	WE	write enable count
field:	17:12	OE	output enable count
field:	11:6	CE	chip enable count
field:	5:0	ADR	address count


[CN3120_MIO_BOOT_LOC_CFG0]
[CN3120_MIO_BOOT_LOC_CFG1]
[CN3120_MIO_BOOT_LOC_ADR]
[CN3120_MIO_BOOT_LOC_DAT]
[CN3120_MIO_BOOT_ERR]
[CN3120_MIO_BOOT_INT]
[CN3120_MIO_BOOT_THR]
[CN3120_MIO_BOOT_BIST_STAT]

