#!/ciena/bin/regdecode64 0x00011800B0000000

[ASX0_RX_PRT_EN]
offset: 0x0000

[ASX0_TX_PRT_EN]
offset: 0x0008

[ASX0_INT_REG]
offset: 0x0010

[ASX0_INT_EN]
offset: 0x0018

[ASX0_RX_CLK_SET0]
offset: 0x0020

[ASX0_RX_CLK_SET1]
offset: 0x0028

[ASX0_RX_CLK_SET2]
offset: 0x0030

[ASX0_PRT_LOOP]
offset: 0x0040

[ASX0_TX_CLK_SET0]
offset: 0x0048

[ASX0_TX_CLK_SET1]
offset: 0x0050

[ASX0_TX_CLK_SET2]
offset: 0x0058

[ASX0_TX_COMP_BYP]
offset: 0x0068

[ASX0_TX_HI_WATER000]
offset: 0x0080

[ASX0_TX_HI_WATER001]
offset: 0x0088

[ASX0_TX_HI_WATER002]
offset: 0x0090

[ASX0_GMII_RX_CLK_SET]
offset: 0x0180

[ASX0_GMII_RX_DAT_SET]
offset: 0x0188

[ASX0_MII_RX_DAT_SET]
offset: 0x0190

