#!/ciena/bin/regdecode64 0x0001180008000000

[GMX0_RX0_INT_REG]
offset: 0x0000

[GMX0_RX0_INT_EN]
offset: 0x0008

[GMX0_PRT0_CFG]
offset: 0x0010

[GMX0_RX0_FRM_CTL]
offset: 0x0018

[GMX0_RX0_FRM_CHK]
offset: 0x0020

[GMX0_RX0_FRM_MIN]
offset: 0x0028

[GMX0_RX0_FRM_MAX]
offset: 0x0030

[GMX0_RX0_JABBER]
offset: 0x0038

[GMX0_RX0_DECISION]
offset: 0x0040

[GMX0_RX0_UDD_SKP]
offset: 0x0048

[GMX0_RX0_STATS_CTL]
offset: 0x0050

[GMX0_RX0_IFG]
offset: 0x0058

[GMX0_RX0_RX_INBND]
offset: 0x0060

[GMX0_RX0_STATS_PKTS]
offset: 0x0080

[GMX0_RX0_STATS_OCTS]
offset: 0x0088

[GMX0_RX0_STATS_PKTS_CTL]
offset: 0x0090

[GMX0_RX0_STATS_OCTS_CTL]
offset: 0x0098

[GMX0_RX0_STATS_PKTS_DMAC]
offset: 0x00A0

[GMX0_RX0_STATS_OCTS_DMAC]
offset: 0x00A8

[GMX0_RX0_STATS_PKTS_DRP]
offset: 0x00B0

[GMX0_RX0_STATS_OCTS_DRP]
offset: 0x00B8

[GMX0_RX0_STATS_PKTS_BAD]
offset: 0x00C0

[GMX0_RX0_ADR_CTL]
offset: 0x0100

[GMX0_RX0_ADR_CAM_EN]
offset: 0x0108

[GMX0_RX0_ADR_CAM0]
offset: 0x0180

[GMX0_RX0_ADR_CAM1]
offset: 0x0188

[GMX0_RX0_ADR_CAM2]
offset: 0x0190

[GMX0_RX0_ADR_CAM3]
offset: 0x0198

[GMX0_RX0_ADR_CAM4]
offset: 0x01A0

[GMX0_RX0_ADR_CAM5]
offset: 0x01A8

[GMX0_TX0_CLK]
offset: 0x0208

[GMX0_TX0_THRESH]
offset: 0x0210

[GMX0_TX0_APPEND]
offset: 0x0218

[GMX0_TX0_SLOT]
offset: 0x0220

[GMX0_TX0_BURST]
offset: 0x0228

[GMX0_SMAC0]
offset: 0x0230

[GMX0_TX0_PAUSE_PKT_TIME]
offset: 0x0238

[GMX0_TX0_MIN_PKT]
offset: 0x0240

[GMX0_TX0_PAUSE_PKT_INTERVAL]
offset: 0x0248

[GMX0_TX0_SOFT_PAUSE]
offset: 0x0250

[GMX0_TX0_PAUSE_TOGO]
offset: 0x0258

[GMX0_TX0_PAUSE_ZERO]
offset: 0x0260

[GMX0_TX0_STATS_CTL]
offset: 0x0268

[GMX0_TX0_CTL]
offset: 0x0270

[GMX0_TX0_STAT0]
offset: 0x0280

[GMX0_TX0_STAT1]
offset: 0x0288

[GMX0_TX0_STAT2]
offset: 0x0290

[GMX0_TX0_STAT3]
offset: 0x0298

[GMX0_TX0_STAT4]
offset: 0x02A0

[GMX0_TX0_STAT5]
offset: 0x02A8

[GMX0_TX0_STAT6]
offset: 0x02B0

[GMX0_TX0_STAT7]
offset: 0x02B8

[GMX0_TX0_STAT8]
offset: 0x02C0

[GMX0_TX0_STAT9]
offset: 0x02C8

[GMX0_BIST]
offset: 0x0400

[GMX0_RX_PRTS]
offset: 0x0410

[GMX0_RX_BP_DROP0]
offset: 0x0420

[GMX0_RX_BP_DROP1]
offset: 0x0428

[GMX0_RX_BP_DROP2]
offset: 0x0430

[GMX0_RX_BP_ON0]
offset: 0x0440

[GMX0_RX_BP_ON1]
offset: 0x0448

[GMX0_RX_BP_ON2]
offset: 0x0450

[GMX0_RX_BP_OFF0]
offset: 0x0460

[GMX0_RX_BP_OFF1]
offset: 0x0468

[GMX0_RX_BP_OFF2]
offset: 0x0470

[GMX0_TX_PRTS]
offset: 0x0480

[GMX0_TX_IFG]
offset: 0x0488

[GMX0_TX_JAM]
offset: 0x0490

[GMX0_TX_COL_ATTEMPT]
offset: 0x0498

[GMX0_TX_PAUSE_PKT_DMAC]
offset: 0x04A0

[GMX0_TX_PAUSE_PKT_TYPE]
offset: 0x04A8

[GMX0_TX_OVR_BP]
offset: 0x04C8

[GMX0_TX_BP]
offset: 0x04D0

[GMX0_TX_CORRUPT]
offset: 0x04D8

[GMX0_RX_PRT_INFO]
offset: 0x04E8

[GMX0_TX_LFSR]
offset: 0x04F8

[GMX0_TX_INT_REG]
offset: 0x0500

[GMX0_TX_INT_EN]
offset: 0x0508

[GMX0_NXA_ADR]
offset: 0x0510

[GMX0_BAD_REG]
offset: 0x0518

[GMX0_STAT_BP]
offset: 0x0520

[GMX0_RX_TX_STATUS]
offset: 0x07E8

[GMX0_INF_MODE]
offset: 0x07F8

[GMX0_RX1_INT_REG]
offset: 0x0800

[GMX0_RX1_INT_EN]
offset: 0x0808

[GMX0_PRT1_CFG]
offset: 0x0810

[GMX0_RX1_FRM_CTL]
offset: 0x0818

[GMX0_RX1_FRM_CHK]
offset: 0x0820

[GMX0_RX1_FRM_MIN]
offset: 0x0828

[GMX0_RX1_FRM_MAX]
offset: 0x0830

[GMX0_RX1_JABBER]
offset: 0x0838

[GMX0_RX1_DECISION]
offset: 0x0840

[GMX0_RX1_UDD_SKP]
offset: 0x0848

[GMX0_RX1_STATS_CTL]
offset: 0x0850

[GMX0_RX1_IFG]
offset: 0x0858

[GMX0_RX1_RX_INBND]
offset: 0x0860

[GMX0_RX1_STATS_PKTS]
offset: 0x0880

[GMX0_RX1_STATS_OCTS]
offset: 0x0888

[GMX0_RX1_STATS_PKTS_CTL]
offset: 0x0890

[GMX0_RX1_STATS_OCTS_CTL]
offset: 0x0898

[GMX0_RX1_STATS_PKTS_DMAC]
offset: 0x08A0

[GMX0_RX1_STATS_OCTS_DMAC]
offset: 0x08A8

[GMX0_RX1_STATS_PKTS_DRP]
offset: 0x08B0

[GMX0_RX1_STATS_OCTS_DRP]
offset: 0x08B8

[GMX0_RX1_STATS_PKTS_BAD]
offset: 0x08C0

[GMX0_RX1_ADR_CTL]
offset: 0x0900

[GMX0_RX1_ADR_CAM_EN]
offset: 0x0908

[GMX0_RX1_ADR_CAM0]
offset: 0x0980

[GMX0_RX1_ADR_CAM1]
offset: 0x0988

[GMX0_RX1_ADR_CAM2]
offset: 0x0990

[GMX0_RX1_ADR_CAM3]
offset: 0x0998

[GMX0_RX1_ADR_CAM4]
offset: 0x09A0

[GMX0_RX1_ADR_CAM5]
offset: 0x09A8

[GMX0_TX1_CLK]
offset: 0x0A08

[GMX0_TX1_THRESH]
offset: 0x0A10

[GMX0_TX1_APPEND]
offset: 0x0A18

[GMX0_TX1_SLOT]
offset: 0x0A20

[GMX0_TX1_BURST]
offset: 0x0A28

[GMX0_SMAC1]
offset: 0x0A30

[GMX0_TX1_PAUSE_PKT_TIME]
offset: 0x0A38

[GMX0_TX1_MIN_PKT]
offset: 0x0A40

[GMX0_TX1_PAUSE_PKT_INTERVAL]
offset: 0x0A48

[GMX0_TX1_SOFT_PAUSE]
offset: 0x0A50

[GMX0_TX1_PAUSE_TOGO]
offset: 0x0A58

[GMX0_TX1_PAUSE_ZERO]
offset: 0x0A60

[GMX0_TX1_STATS_CTL]
offset: 0x0A68

[GMX0_TX1_CTL]
offset: 0x0A70

[GMX0_TX1_STAT0]
offset: 0x0A80

[GMX0_TX1_STAT1]
offset: 0x0A88

[GMX0_TX1_STAT2]
offset: 0x0A90

[GMX0_TX1_STAT3]
offset: 0x0A98

[GMX0_TX1_STAT4]
offset: 0x0AA0

[GMX0_TX1_STAT5]
offset: 0x0AA8

[GMX0_TX1_STAT6]
offset: 0x0AB0

[GMX0_TX1_STAT7]
offset: 0x0AB8

[GMX0_TX1_STAT8]
offset: 0x0AC0

[GMX0_TX1_STAT9]
offset: 0x0AC8

[GMX0_RX2_INT_REG]
offset: 0x1000

[GMX0_RX2_INT_EN]
offset: 0x1008

[GMX0_PRT2_CFG]
offset: 0x1010

[GMX0_RX2_FRM_CTL]
offset: 0x1018

[GMX0_RX2_FRM_CHK]
offset: 0x1020

[GMX0_RX2_FRM_MIN]
offset: 0x1028

[GMX0_RX2_FRM_MAX]
offset: 0x1030

[GMX0_RX2_JABBER]
offset: 0x1038

[GMX0_RX2_DECISION]
offset: 0x1040

[GMX0_RX2_UDD_SKP]
offset: 0x1048

[GMX0_RX2_STATS_CTL]
offset: 0x1050

[GMX0_RX2_IFG]
offset: 0x1058

[GMX0_RX2_RX_INBND]
offset: 0x1060

[GMX0_RX2_STATS_PKTS]
offset: 0x1080

[GMX0_RX2_STATS_OCTS]
offset: 0x1088

[GMX0_RX2_STATS_PKTS_CTL]
offset: 0x1090

[GMX0_RX2_STATS_OCTS_CTL]
offset: 0x1098

[GMX0_RX2_STATS_PKTS_DMAC]
offset: 0x10A0

[GMX0_RX2_STATS_OCTS_DMAC]
offset: 0x10A8

[GMX0_RX2_STATS_PKTS_DRP]
offset: 0x10B0

[GMX0_RX2_STATS_OCTS_DRP]
offset: 0x10B8

[GMX0_RX2_STATS_PKTS_BAD]
offset: 0x10C0

[GMX0_RX2_ADR_CTL]
offset: 0x1100

[GMX0_RX2_ADR_CAM_EN]
offset: 0x1108

[GMX0_RX2_ADR_CAM0]
offset: 0x1180

[GMX0_RX2_ADR_CAM1]
offset: 0x1188

[GMX0_RX2_ADR_CAM2]
offset: 0x1190

[GMX0_RX2_ADR_CAM3]
offset: 0x1198

[GMX0_RX2_ADR_CAM4]
offset: 0x11A0

[GMX0_RX2_ADR_CAM5]
offset: 0x11A8

[GMX0_TX2_CLK]
offset: 0x1208

[GMX0_TX2_THRESH]
offset: 0x1210

[GMX0_TX2_APPEND]
offset: 0x1218

[GMX0_TX2_SLOT]
offset: 0x1220

[GMX0_TX2_BURST]
offset: 0x1228

[GMX0_SMAC2]
offset: 0x1230

[GMX0_TX2_PAUSE_PKT_TIME]
offset: 0x1238

[GMX0_TX2_MIN_PKT]
offset: 0x1240

[GMX0_TX2_PAUSE_PKT_INTERVAL]
offset: 0x1248

[GMX0_TX2_SOFT_PAUSE]
offset: 0x1250

[GMX0_TX2_PAUSE_TOGO]
offset: 0x1258

[GMX0_TX2_PAUSE_ZERO]
offset: 0x1260

[GMX0_TX2_STATS_CTL]
offset: 0x1268

[GMX0_TX2_CTL]
offset: 0x1270

[GMX0_TX2_STAT0]
offset: 0x1280

[GMX0_TX2_STAT1]
offset: 0x1288

[GMX0_TX2_STAT2]
offset: 0x1290

[GMX0_TX2_STAT3]
offset: 0x1298

[GMX0_TX2_STAT4]
offset: 0x12A0

[GMX0_TX2_STAT5]
offset: 0x12A8

[GMX0_TX2_STAT6]
offset: 0x12B0

[GMX0_TX2_STAT7]
offset: 0x12B8

[GMX0_TX2_STAT8]
offset: 0x12C0

[GMX0_TX2_STAT9]
offset: 0x12C8

