#!/ciena/bin/regdecode UIO Driver for Cavium 3120 GPIO

# base 0x0001070000000000 + 0x800 = 0x0001070000000800

pad: 0x800

[CAVIUM3120GPIO_BIT_CFG0]
name: GPIO bit configuration Registers
width: 64
field:	63:12	RESERVED
field:	11:8	FIL_SEL
field:	7:4	FIL_CNT
field:	3	INT_TYPE
field:	2	INT_EN
field:	1	RX_XOR
field:	0	TX_OE

[CAVIUM3120GPIO_BIT_CFG1]
name: GPIO bit configuration Registers
width: 64
field:	63:12	RESERVED
field:	11:8	FIL_SEL
field:	7:4	FIL_CNT
field:	3	INT_TYPE
field:	2	INT_EN
field:	1	RX_XOR
field:	0	TX_OE

[CAVIUM3120GPIO_BIT_CFG2]
name: GPIO bit configuration Registers
width: 64
field:	63:12	RESERVED
field:	11:8	FIL_SEL
field:	7:4	FIL_CNT
field:	3	INT_TYPE
field:	2	INT_EN
field:	1	RX_XOR
field:	0	TX_OE

[CAVIUM3120GPIO_BIT_CFG3]
name: GPIO bit configuration Registers
width: 64
field:	63:12	RESERVED
field:	11:8	FIL_SEL
field:	7:4	FIL_CNT
field:	3	INT_TYPE
field:	2	INT_EN
field:	1	RX_XOR
field:	0	TX_OE

[CAVIUM3120GPIO_BIT_CFG4]
name: GPIO bit configuration Registers
width: 64
field:	63:12	RESERVED
field:	11:8	FIL_SEL
field:	7:4	FIL_CNT
field:	3	INT_TYPE
field:	2	INT_EN
field:	1	RX_XOR
field:	0	TX_OE

[CAVIUM3120GPIO_BIT_CFG5]
name: GPIO bit configuration Registers
width: 64
field:	63:12	RESERVED
field:	11:8	FIL_SEL
field:	7:4	FIL_CNT
field:	3	INT_TYPE
field:	2	INT_EN
field:	1	RX_XOR
field:	0	TX_OE

[CAVIUM3120GPIO_BIT_CFG6]
name: GPIO bit configuration Registers
width: 64
field:	63:12	RESERVED
field:	11:8	FIL_SEL
field:	7:4	FIL_CNT
field:	3	INT_TYPE
field:	2	INT_EN
field:	1	RX_XOR
field:	0	TX_OE

[CAVIUM3120GPIO_BIT_CFG7]
name: GPIO bit configuration Registers
width: 64
field:	63:12	RESERVED
field:	11:8	FIL_SEL
field:	7:4	FIL_CNT
field:	3	INT_TYPE
field:	2	INT_EN
field:	1	RX_XOR
field:	0	TX_OE

[CAVIUM3120GPIO_BIT_CFG8]
name: GPIO bit configuration Registers
width: 64
field:	63:12	RESERVED
field:	11:8	FIL_SEL
field:	7:4	FIL_CNT
field:	3	INT_TYPE
field:	2	INT_EN
field:	1	RX_XOR
field:	0	TX_OE

[CAVIUM3120GPIO_BIT_CFG9]
name: GPIO bit configuration Registers
width: 64
field:	63:12	RESERVED
field:	11:8	FIL_SEL
field:	7:4	FIL_CNT
field:	3	INT_TYPE
field:	2	INT_EN
field:	1	RX_XOR
field:	0	TX_OE

[CAVIUM3120GPIO_BIT_CFG10]
name: GPIO bit configuration Registers
width: 64
field:	63:12	RESERVED
field:	11:8	FIL_SEL
field:	7:4	FIL_CNT
field:	3	INT_TYPE
field:	2	INT_EN
field:	1	RX_XOR
field:	0	TX_OE

[CAVIUM3120GPIO_BIT_CFG11]
name: GPIO bit configuration Registers
width: 64
field:	63:12	RESERVED
field:	11:8	FIL_SEL
field:	7:4	FIL_CNT
field:	3	INT_TYPE
field:	2	INT_EN
field:	1	RX_XOR
field:	0	TX_OE

[CAVIUM3120GPIO_BIT_CFG12]
name: GPIO bit configuration Registers
width: 64
field:	63:12	RESERVED
field:	11:8	FIL_SEL
field:	7:4	FIL_CNT
field:	3	INT_TYPE
field:	2	INT_EN
field:	1	RX_XOR
field:	0	TX_OE

[CAVIUM3120GPIO_BIT_CFG13]
name: GPIO bit configuration Registers
width: 64
field:	63:12	RESERVED
field:	11:8	FIL_SEL
field:	7:4	FIL_CNT
field:	3	INT_TYPE
field:	2	INT_EN
field:	1	RX_XOR
field:	0	TX_OE

[CAVIUM3120GPIO_BIT_CFG14]
name: GPIO bit configuration Registers
width: 64
field:	63:12	RESERVED
field:	11:8	FIL_SEL
field:	7:4	FIL_CNT
field:	3	INT_TYPE
field:	2	INT_EN
field:	1	RX_XOR
field:	0	TX_OE

[CAVIUM3120GPIO_BIT_CFG15]
name: GPIO bit configuration Registers
width: 64
field:	63:12	RESERVED
field:	11:8	FIL_SEL
field:	7:4	FIL_CNT
field:	3	INT_TYPE
field:	2	INT_EN
field:	1	RX_XOR
field:	0	TX_OE

[CAVIUM3120GPIO_RX_DAT]
width: 64
field:	63:24	RESERVED
field:	23	GPIO_23
field:	22	GPIO_22
field:	21	GPIO_21
field:	20	GPIO_20
field:	19	GPIO_19
field:	18	GPIO_18
field:	17	GPIO_17
field:	16	GPIO_16
field:	15	GPIO_15
field:	14	GPIO_14
field:	13	GPIO_13
field:	12	GPIO_12
field:	11	GPIO_11
field:	10	GPIO_10
field:	9	GPIO_9
field:	8	GPIO_8
field:	7	GPIO_7
field:	6	GPIO_6
field:	5	GPIO_5
field:	4	GPIO_4
field:	3	GPIO_3
field:	2	GPIO_2
field:	1	GPIO_1
field:	0	GPIO_0

[CAVIUM3120GPIO_TX_SET]
width: 64
field:	63:24	RESERVED
field:	23	GPIO_23
field:	22	GPIO_22
field:	21	GPIO_21
field:	20	GPIO_20
field:	19	GPIO_19
field:	18	GPIO_18
field:	17	GPIO_17
field:	16	GPIO_16
field:	15	GPIO_15
field:	14	GPIO_14
field:	13	GPIO_13
field:	12	GPIO_12
field:	11	GPIO_11
field:	10	GPIO_10
field:	9	GPIO_9
field:	8	GPIO_8
field:	7	GPIO_7
field:	6	GPIO_6
field:	5	GPIO_5
field:	4	GPIO_4
field:	3	GPIO_3
field:	2	GPIO_2
field:	1	GPIO_1
field:	0	GPIO_0

[CAVIUM3120GPIO_TX_CLR]
width: 64
field:	63:24	RESERVED
field:	23	GPIO_23
field:	22	GPIO_22
field:	21	GPIO_21
field:	20	GPIO_20
field:	19	GPIO_19
field:	18	GPIO_18
field:	17	GPIO_17
field:	16	GPIO_16
field:	15	GPIO_15
field:	14	GPIO_14
field:	13	GPIO_13
field:	12	GPIO_12
field:	11	GPIO_11
field:	10	GPIO_10
field:	9	GPIO_9
field:	8	GPIO_8
field:	7	GPIO_7
field:	6	GPIO_6
field:	5	GPIO_5
field:	4	GPIO_4
field:	3	GPIO_3
field:	2	GPIO_2
field:	1	GPIO_1
field:	0	GPIO_0

[CAVIUM3120GPIO_INT_CLR]
width: 64
field:	63:16	RESERVED
field:	15	GPIO_15
field:	14	GPIO_14
field:	13	GPIO_13
field:	12	GPIO_12
field:	11	GPIO_11
field:	10	GPIO_10
field:	9	GPIO_9
field:	8	GPIO_8
field:	7	GPIO_7
field:	6	GPIO_6
field:	5	GPIO_5
field:	4	GPIO_4
field:	3	GPIO_3
field:	2	GPIO_2
field:	1	GPIO_1
field:	0	GPIO_0

[CAVIUM3120GPIO_DBG_ENA]
width: 64
field:	63:21	RESERVED
field:	20	GPIO_20
field:	19	GPIO_19
field:	18	GPIO_18
field:	17	GPIO_17
field:	16	GPIO_16
field:	15	GPIO_15
field:	14	GPIO_14
field:	13	GPIO_13
field:	12	GPIO_12
field:	11	GPIO_11
field:	10	GPIO_10
field:	9	GPIO_9
field:	8	GPIO_8
field:	7	GPIO_7
field:	6	GPIO_6
field:	5	GPIO_5
field:	4	GPIO_4
field:	3	GPIO_3
field:	2	GPIO_2
field:	1	GPIO_1
field:	0	GPIO_0

[CAVIUM3120GPIO_BOOT_ENA]
width: 64
field:	63:12	RESERVED
field:	11	GPIO_11
field:	10	GPIO_10
field:	9	GPIO_9
field:	8	GPIO_8
field:	7:0	--


pad: 0x50


[CAVIUM3120GPIO_XBIT_CFG16]
name: GPIO bit configuration Registers
width: 64
field:	63:12	RESERVED
field:	11:8	FIL_SEL
field:	7:4	FIL_CNT
field:	3:2	--
field:	1	RX_XOR
field:	0	TX_OE

[CAVIUM3120GPIO_XBIT_CFG17]
name: GPIO bit configuration Registers
width: 64
field:	63:12	RESERVED
field:	11:8	FIL_SEL
field:	7:4	FIL_CNT
field:	3:2	--
field:	1	RX_XOR
field:	0	TX_OE

[CAVIUM3120GPIO_XBIT_CFG18]
name: GPIO bit configuration Registers
width: 64
field:	63:12	RESERVED
field:	11:8	FIL_SEL
field:	7:4	FIL_CNT
field:	3:2	--
field:	1	RX_XOR
field:	0	TX_OE

[CAVIUM3120GPIO_XBIT_CFG19]
name: GPIO bit configuration Registers
width: 64
field:	63:12	RESERVED
field:	11:8	FIL_SEL
field:	7:4	FIL_CNT
field:	3:2	--
field:	1	RX_XOR
field:	0	TX_OE

[CAVIUM3120GPIO_XBIT_CFG20]
name: GPIO bit configuration Registers
width: 64
field:	63:12	RESERVED
field:	11:8	FIL_SEL
field:	7:4	FIL_CNT
field:	3:2	--
field:	1	RX_XOR
field:	0	TX_OE

[CAVIUM3120GPIO_XBIT_CFG21]
name: GPIO bit configuration Registers
width: 64
field:	63:12	RESERVED
field:	11:8	FIL_SEL
field:	7:4	FIL_CNT
field:	3:2	--
field:	1	RX_XOR
field:	0	TX_OE

[CAVIUM3120GPIO_XBIT_CFG22]
name: GPIO bit configuration Registers
width: 64
field:	63:12	RESERVED
field:	11:8	FIL_SEL
field:	7:4	FIL_CNT
field:	3:2	--
field:	1	RX_XOR
field:	0	TX_OE

[CAVIUM3120GPIO_XBIT_CFG23]
name: GPIO bit configuration Registers
width: 64
field:	63:12	RESERVED
field:	11:8	FIL_SEL
field:	7:4	FIL_CNT
field:	3:2	--
field:	1	RX_XOR
field:	0	TX_OE

