#!/ciena/bin/regdecode64 0x00011800C8000000

[CTL_STATUS]
name:
width: 64
offset: 0x00
field:	63:28	Reserved28
field:	27:23	DNUM        RO
field:	21:15	PBUS        RO
field:	14:13	QLM_CFG     RO
value:	0	_2_lanes
value:	3	_4_lanes
field:	12	LANE_SWP   R/W  
field:	11	PM_XTOFF   R/W
field:	10	PM_XPME    R/W
field:	9	OB_P_CMD   R/W
field:	8:7	Reserved7
field:	6	NF_ECRC
field:	5	DLY_ONE
field:	4	LNK_ENB    R/W
field:	3	RO_CTLP    R/W
field:	2	Reserved2
field:	1	INV_ECRC   R/W
field:	0	INV_LCRC   R/W


[DBG_INFO]
name:
width: 64
offset: 0x08

[BIST_STATUS]
name:
width: 64
offset: 0x18

[DIAG_STATUS]
name:
width: 64
offset: 0x20

[CFG_WR]
name:
width: 64
offset: 0x28
field: 63:32 DATA
field: 31:0  ADDR

[CFG_RD]
name:
width: 64
offset: 0x30
field: 63:32 DATA
field: 31:0  ADDR

[DBG_INFO_EN]
name:
width: 64
offset: 0xA0

[CTL_STATUS2]
name:
width: 64
offset: 0x400

[BIST_STATUS2]
name:
width: 64
offset: 0x418

