#!/ciena/bin/regdecode UIO Driver for Cavium 52xx MIO BOOT
#
# hand-crafted from arch/mips/include/asm/octeon/cvmx-mio-defs.h
#
# base 0x0001180000000000

[CVMX_MIO_BOOT_REG_CFGX_0]
width: 64
field:	63:44	RESERVED
field:	43:42	DMACK
field:	41:40	TIM_MULT
field:	39:37	RD_DLY
field:	36:36	SAM
field:	35:34	WE_EXT
field:	33:32	OE_EXT
field:	31:31	EN
field:	30:30	ORBIT
field:	29:29	ALE
field:	28:28	WIDTH
field:	27:16	SIZE
field:	15:0	BASE

[CVMX_MIO_BOOT_REG_CFGX_1]
width: 64
field:	63:44	RESERVED
field:	43:42	DMACK
field:	41:40	TIM_MULT
field:	39:37	RD_DLY
field:	36:36	SAM
field:	35:34	WE_EXT
field:	33:32	OE_EXT
field:	31:31	EN
field:	30:30	ORBIT
field:	29:29	ALE
field:	28:28	WIDTH
field:	27:16	SIZE
field:	15:0	BASE

[CVMX_MIO_BOOT_REG_CFGX_2]
width: 64
field:	63:44	RESERVED
field:	43:42	DMACK
field:	41:40	TIM_MULT
field:	39:37	RD_DLY
field:	36:36	SAM
field:	35:34	WE_EXT
field:	33:32	OE_EXT
field:	31:31	EN
field:	30:30	ORBIT
field:	29:29	ALE
field:	28:28	WIDTH
field:	27:16	SIZE
field:	15:0	BASE

[CVMX_MIO_BOOT_REG_CFGX_3]
width: 64
field:	63:44	RESERVED
field:	43:42	DMACK
field:	41:40	TIM_MULT
field:	39:37	RD_DLY
field:	36:36	SAM
field:	35:34	WE_EXT
field:	33:32	OE_EXT
field:	31:31	EN
field:	30:30	ORBIT
field:	29:29	ALE
field:	28:28	WIDTH
field:	27:16	SIZE
field:	15:0	BASE

[CVMX_MIO_BOOT_REG_CFGX_4]
width: 64
field:	63:44	RESERVED
field:	43:42	DMACK
field:	41:40	TIM_MULT
field:	39:37	RD_DLY
field:	36:36	SAM
field:	35:34	WE_EXT
field:	33:32	OE_EXT
field:	31:31	EN
field:	30:30	ORBIT
field:	29:29	ALE
field:	28:28	WIDTH
field:	27:16	SIZE
field:	15:0	BASE

[CVMX_MIO_BOOT_REG_CFGX_5]
width: 64
field:	63:44	RESERVED
field:	43:42	DMACK
field:	41:40	TIM_MULT
field:	39:37	RD_DLY
field:	36:36	SAM
field:	35:34	WE_EXT
field:	33:32	OE_EXT
field:	31:31	EN
field:	30:30	ORBIT
field:	29:29	ALE
field:	28:28	WIDTH
field:	27:16	SIZE
field:	15:0	BASE

[CVMX_MIO_BOOT_REG_CFGX_6]
width: 64
field:	63:44	RESERVED
field:	43:42	DMACK
field:	41:40	TIM_MULT
field:	39:37	RD_DLY
field:	36:36	SAM
field:	35:34	WE_EXT
field:	33:32	OE_EXT
field:	31:31	EN
field:	30:30	ORBIT
field:	29:29	ALE
field:	28:28	WIDTH
field:	27:16	SIZE
field:	15:0	BASE

[CVMX_MIO_BOOT_REG_CFGX_7]
width: 64
field:	63:44	RESERVED
field:	43:42	DMACK
field:	41:40	TIM_MULT
field:	39:37	RD_DLY
field:	36:36	SAM
field:	35:34	WE_EXT
field:	33:32	OE_EXT
field:	31:31	EN
field:	30:30	ORBIT
field:	29:29	ALE
field:	28:28	WIDTH
field:	27:16	SIZE
field:	15:0	BASE

[CVMX_MIO_BOOT_REG_TIMX_0]
width: 64
field:	63:63	PAGEM
field:	62:62	WAITM
field:	61:60	PAGES
field:	59:54	ALE
field:	53:48	PAGE
field:	47:42	WAIT
field:	41:36 PAUSE
field:	35:30	WR_HLD
field:	29:24	RD_HLD
field:	23:18	WE
field:	17:12	OE
field:	11:6	CE
field:	5:0	ADR

[CVMX_MIO_BOOT_REG_TIMX_1]
width: 64
field:	63:63	PAGEM
field:	62:62	WAITM
field:	61:60	PAGES
field:	59:54	ALE
field:	53:48	PAGE
field:	47:42	WAIT
field:	41:36 PAUSE
field:	35:30	WR_HLD
field:	29:24	RD_HLD
field:	23:18	WE
field:	17:12	OE
field:	11:6	CE
field:	5:0	ADR

[CVMX_MIO_BOOT_REG_TIMX_2]
width: 64
field:	63:63	PAGEM
field:	62:62	WAITM
field:	61:60	PAGES
field:	59:54	ALE
field:	53:48	PAGE
field:	47:42	WAIT
field:	41:36 PAUSE
field:	35:30	WR_HLD
field:	29:24	RD_HLD
field:	23:18	WE
field:	17:12	OE
field:	11:6	CE
field:	5:0	ADR

[CVMX_MIO_BOOT_REG_TIMX_3]
width: 64
field:	63:63	PAGEM
field:	62:62	WAITM
field:	61:60	PAGES
field:	59:54	ALE
field:	53:48	PAGE
field:	47:42	WAIT
field:	41:36 PAUSE
field:	35:30	WR_HLD
field:	29:24	RD_HLD
field:	23:18	WE
field:	17:12	OE
field:	11:6	CE
field:	5:0	ADR

[CVMX_MIO_BOOT_REG_TIMX_4]
width: 64
field:	63:63	PAGEM
field:	62:62	WAITM
field:	61:60	PAGES
field:	59:54	ALE
field:	53:48	PAGE
field:	47:42	WAIT
field:	41:36 PAUSE
field:	35:30	WR_HLD
field:	29:24	RD_HLD
field:	23:18	WE
field:	17:12	OE
field:	11:6	CE
field:	5:0	ADR

[CVMX_MIO_BOOT_REG_TIMX_5]
width: 64
field:	63:63	PAGEM
field:	62:62	WAITM
field:	61:60	PAGES
field:	59:54	ALE
field:	53:48	PAGE
field:	47:42	WAIT
field:	41:36 PAUSE
field:	35:30	WR_HLD
field:	29:24	RD_HLD
field:	23:18	WE
field:	17:12	OE
field:	11:6	CE
field:	5:0	ADR

[CVMX_MIO_BOOT_REG_TIMX_6]
width: 64
field:	63:63	PAGEM
field:	62:62	WAITM
field:	61:60	PAGES
field:	59:54	ALE
field:	53:48	PAGE
field:	47:42	WAIT
field:	41:36 PAUSE
field:	35:30	WR_HLD
field:	29:24	RD_HLD
field:	23:18	WE
field:	17:12	OE
field:	11:6	CE
field:	5:0	ADR

[CVMX_MIO_BOOT_REG_TIMX_7]
width: 64
field:	63:63	PAGEM
field:	62:62	WAITM
field:	61:60	PAGES
field:	59:54	ALE
field:	53:48	PAGE
field:	47:42	WAIT
field:	41:36 PAUSE
field:	35:30	WR_HLD
field:	29:24	RD_HLD
field:	23:18	WE
field:	17:12	OE
field:	11:6	CE
field:	5:0	ADR

[CVMX_MIO_BOOT_LOC_CFGX_0]
width: 64
field:	63:32	RESERVED_32_63
field:	31:31	EN
field:	30:28	RESERVED_28_30
field:	27:3	BASE
field:	2:0	RESERVED_0_2

[CVMX_MIO_BOOT_LOC_CFGX_1]
width: 64
field:	63:32	RESERVED_32_63
field:	31:31	EN
field:	30:28	RESERVED_28_30
field:	27:3	BASE
field:	2:0	RESERVED_0_2

[CVMX_MIO_BOOT_LOC_ADR]
width: 64
field:	63:8	RESERVED_8_63
field:	7:3	ADR
field:	2:0	RESERVED_0_2

[CVMX_MIO_BOOT_LOC_DAT]
width: 64
field:	63:0	DATA

[CVMX_MIO_BOOT_ERR]
width: 64
field:	63:2	RESERVED_2_63
field:	1:1	WAIT_ERR
field:	0:0	ADR_ERR

[CVMX_MIO_BOOT_INT]
width: 64
field:	63:2	RESERVED_2_63
field:	1:1	WAIT_INT
field:	0:0	ADR_INT

[CVMX_MIO_BOOT_THR]
width: 64
field:	63:22	RESERVED_22_63
field:	21:16	DMA_THR
field:	15:14	RESERVED_14_15
field:	13:8	FIF_CNT
field:	7:6	RESERVED_6_7
field:	5:0	FIF_THR

[CVMX_MIO_BOOT_COMP]
width: 64
field:	63:12	RESERVED
field:	11:6	PCTL
field:	5:1	NCTL

[CVMX_MIO_BOOT_PIN_DEFS]
width: 64
field:	63:16	RESERVED_16_63
field:	15:15	ALE
field:	14:14	WIDTH
field:	13:13	RESERVED_13_13
field:	12:12	DMACK_P1
field:	11:11	DMACK_P0
field:	10:9	TERM
field:	8:8	NAND
field:	7:0	RESERVED_0_7

pad: 0x30

[CVMX_MIO_BOOT_BIST_STAT]
width: 64
field:	63:6	RESERVED
field:	5:4	NDF
field:	3	NCBO_0
field:	2	DMA
field:	1	LOC
field:	0	NCBI

[CVMX_MIO_BOOT_DMA_CFGX_0]
width: 64
field:	63:63	EN
field:	62:62	RW
field:	61:61	CLR
field:	60:60	RESERVED
field:	59:59	SWAP32
field:	58:58	SWAP16
field:	57:57	SWAP8
field:	56:56	ENDIAN
field:	55:36	SIZE
field:	35:0	ADR

[CVMX_MIO_BOOT_DMA_CFGX_1]
width: 64
field:	63:63	EN
field:	62:62	RW
field:	61:61	CLR
field:	60:60	RESERVED
field:	59:59	SWAP32
field:	58:58	SWAP16
field:	57:57	SWAP8
field:	56:56	ENDIAN
field:	55:36	SIZE
field:	35:0	ADR

[CVMX_MIO_BOOT_DMA_CFGX_2]
width: 64
field:	63:63	EN
field:	62:62	RW
field:	61:61	CLR
field:	60:60	RESERVED
field:	59:59	SWAP32
field:	58:58	SWAP16
field:	57:57	SWAP8
field:	56:56	ENDIAN
field:	55:36	SIZE
field:	35:0	ADR

[CVMX_MIO_BOOT_DMA_CFGX_3]
width: 64
field:	63:63	EN
field:	62:62	RW
field:	61:61	CLR
field:	60:60	RESERVED
field:	59:59	SWAP32
field:	58:58	SWAP16
field:	57:57	SWAP8
field:	56:56	ENDIAN
field:	55:36	SIZE
field:	35:0	ADR

[CVMX_MIO_BOOT_DMA_TIMX_0]
width: 64
field:	63:63	DMACK_PI
field:	62:62	DMARQ_PI
field:	61:60	TIM_MULT
field:	59:57	RD_DLY
field:	56:56	DDR
field:	55:55	WIDTH
field:	54:48	RESERVED_48_54
field:	47:42	PAUSE
field:	41:36	DMACK_H
field:	35:30	WE_N
field:	29:24	WE_A
field:	23:18	OE_N
field:	17:12	OE_A
field:	11:6	DMACK_S
field:	5:0	DMARQ

[CVMX_MIO_BOOT_DMA_TIMX_1]
width: 64
field:	63:63	DMACK_PI
field:	62:62	DMARQ_PI
field:	61:60	TIM_MULT
field:	59:57	RD_DLY
field:	56:56	DDR
field:	55:55	WIDTH
field:	54:48	RESERVED_48_54
field:	47:42	PAUSE
field:	41:36	DMACK_H
field:	35:30	WE_N
field:	29:24	WE_A
field:	23:18	OE_N
field:	17:12	OE_A
field:	11:6	DMACK_S
field:	5:0	DMARQ

[CVMX_MIO_BOOT_DMA_TIMX_2]
width: 64
field:	63:63	DMACK_PI
field:	62:62	DMARQ_PI
field:	61:60	TIM_MULT
field:	59:57	RD_DLY
field:	56:56	DDR
field:	55:55	WIDTH
field:	54:48	RESERVED_48_54
field:	47:42	PAUSE
field:	41:36	DMACK_H
field:	35:30	WE_N
field:	29:24	WE_A
field:	23:18	OE_N
field:	17:12	OE_A
field:	11:6	DMACK_S
field:	5:0	DMARQ

[CVMX_MIO_BOOT_DMA_INTX_0]
width: 64
field:	63:2	RESERVED_2_63
field:	1:1	DMARQ
field:	0:0	DONE

[CVMX_MIO_BOOT_DMA_INTX_1]
width: 64
field:	63:2	RESERVED_2_63
field:	1:1	DMARQ
field:	0:0	DONE

[CVMX_MIO_BOOT_DMA_INTX_2]
width: 64
field:	63:2	RESERVED_2_63
field:	1:1	DMARQ
field:	0:0	DONE

[CVMX_MIO_BOOT_DMA_INT_ENX_0]
width: 64
field:	63:2	RESERVED_2_63
field:	1:1	DMARQ
field:	0:0	DONE

[CVMX_MIO_BOOT_DMA_INT_ENX_1]
width: 64
field:	63:2	RESERVED_2_63
field:	1:1	DMARQ
field:	0:0	DONE

[CVMX_MIO_BOOT_DMA_INT_ENX_2]
width: 64
field:	63:2	RESERVED_2_63
field:	1:1	DMARQ
field:	0:0	DONE
