Merge
Use the Merge tab to combine two or more circuits that are aligned in path but are separate circuits because of different circuit IDs or conflicting parameters. A merge combines a single master circuit with one or more circuits.
The circuits that appear in the Merge tab are the circuits available for merging, which are all of the circuits in the network except the following:
The "master" circuit, which is the circuit chosen on the Circuit tab for editing
Circuits that are a different circuit size than the master circuit
Circuits that have a different VLAN, Service Level Agreement (SLA), or monitor designation than the master circuit
Circuits with a CREATING, DELETING, DROP_PENDING, or ROLL_PENDING status
Displays the name of the circuit. The circuit name can be manually assigned or automatically generated.
Circuit types are HOP (high-order circuit), LOP (low-order circuit), VCT (VC low-order tunnel), VCA (VC low-order aggregation point), OCHNC, HOP_v (high-order VCAT circuit), or LOP_v (low-order VCAT circuit).
Circuit size. Low-order circuits are VC11 (with XC-VXC-10G card only), VC12, and VC3. High-order circuit sizes are VC4, VC4-3c, VC4-4c, VC4-6c, VC4-8c, VC4-16c, and VC4-64c. OCHNC sizes are Equipped not specific, Multi-rate, 2.5 Gbps No FEC, 2.5 Gbps FEC, 10 Gbps No FEC, and 10 Gbps FEC. High-order VCAT circuits are VC4-2v and VC4-4c-2v. Low-order VCAT circuits are VC3-2v.
Displays the OCHNC direction, either East to West or West to East.
Displays the type of circuit protection. See Circuit Protection Types for descriptions.
Displays the circuit status. See Circuit Statuses for descriptions.
Displays the circuit source in the format: node/slot/port "port name" virtual container/tributary unit group. (The port name appears in quotes.) Node and slot always display; port "port name"/virtual container/tributary unit group might display, depending on the source card, circuit type, and whether a name is assigned to the port. If the circuit size is a concatenated size (VC4-2c, VC4-4c, VC4-8c, etc.) VCs used in the circuit are indicated by an ellipsis, for example, VC4-7..9 (VCs 7, 8, and 9) or VC4-10..12 (VC 10, 11, and 12).
Displays the circuit destination in the same format (node/slot/port "port name"/virtual container/tributary unit group) as the circuit source.
Displays the number of internode links that constitute the circuit. Right-clicking the column displays a shortcut menu from which you can choose to show or hide circuit span detail.
Displays the circuit state. See Circuit States and Circuit Creation for descriptions.
Updates the Merge tab with current circuits that are available for merging.
If checked, changes the circuit view in the graphic area to show circuit routing information including source slot, port, and VC. The detailed view also shows working and protect circuit paths. If 802.17 RPR mode is enabled, the port displays as pRPR East or pRPR West.
If checked, displays any low-order path tunnels that carry the low-order path circuit. If the circuit is not carried by a low-order path tunnel, no changes appear when the box is checked.
If checked, hides the TXP and MXP connections on which high-order and low-order circuits are routed, showing only the logical STM-N links. This check box is available only when circuits are routed on TXP or MXP cards provisioned in section or line mode.