; Device Id            : ZL30806
; GUI Version          : 1.3.1
; File Generation Date : Wednesday, August 26, 2020 3:43:07 PM
;======================================================================

; NOTE:
; This is an incremental configuration script.
; For proper device operation, all register write and wait commands in
; this file must be performed in the sequence listed.

;======================================================================

; Configuration script commands

; 1.  Register Write Command:
;        X , <register_address> , <data_bytes>
;        Both <register_address> and <data_bytes> are in hexadecimal
;        format and must have the "0x" prefix.
;        The register_address contains the page number and page offset.
;        The page number is stored in register_address[14:7].
;        The page offset is stored in register_address[6:0].

; 2.  Wait Command:
;        W , <time_microseconds>
;        The wait time is specified in microseconds.

;======================================================================

; The following lines are used only for the evaluation board GUI configuration:

; Master Clock Nominal Freq MHz = 125
; VDDO01 = 3.3 V, VDDO23 = 3.3 V, VDDO45 = 3.3 V, VDDO67 = 3.3 V
; LoadCap HPOUT0=5.00, HPOUT1=5.00, HPOUT2=5.00, HPOUT3=5.00, HPOUT4=5.00, HPOUT5=5.00, HPOUT6=5.00, HPOUT7=5.00

;======================================================================

; Register Configuration Start


;======================================================================
; Register Configuration Start

X , 0x0480  , 0x10                        ;  hp_ctrl_1                   
X , 0x04B0  , 0x20                        ;  hp_ctrl_2                   

X , 0x0582  , 0x00                        ;  ref_mb_mask                 
X , 0x0583  , 0x01                        ;  ref_mb_mask                 
X , 0x0584  , 0x02                        ;  ref_mb_sem                  
W , 20000 
X , 0x0585  , 0x07                        ;  ref0p_freq_base             
X , 0x0586  , 0xD0                        ;  ref0p_freq_base             
X , 0x0598  , 0xCB                        ;  ref0p_pfm_disqualify        
X , 0x0599  , 0x20                        ;  ref0p_pfm_disqualify        
X , 0x0584  , 0x01                        ;  ref_mb_sem                  
W , 20000 

X , 0x0582  , 0x00                        ;  ref_mb_mask                 
X , 0x0583  , 0x02                        ;  ref_mb_mask                 
X , 0x0584  , 0x02                        ;  ref_mb_sem                  
W , 20000 
X , 0x0585  , 0x61                        ;  ref0n_freq_base             
X , 0x0586  , 0xA8                        ;  ref0n_freq_base             
X , 0x0587  , 0x03                        ;  ref0n_freq_mult             
X , 0x0588  , 0xE8                        ;  ref0n_freq_mult             
X , 0x0598  , 0xCB                        ;  ref0n_pfm_disqualify        
X , 0x0599  , 0x20                        ;  ref0n_pfm_disqualify        
X , 0x0584  , 0x01                        ;  ref_mb_sem                  
W , 20000 

X , 0x0582  , 0x00                        ;  ref_mb_mask                 
X , 0x0583  , 0x04                        ;  ref_mb_mask                 
X , 0x0584  , 0x02                        ;  ref_mb_sem                  
W , 20000 
X , 0x0585  , 0x61                        ;  ref1p_freq_base             
X , 0x0586  , 0xA8                        ;  ref1p_freq_base             
X , 0x0587  , 0x03                        ;  ref1p_freq_mult             
X , 0x0588  , 0xE8                        ;  ref1p_freq_mult             
X , 0x0598  , 0xCB                        ;  ref1p_pfm_disqualify        
X , 0x0599  , 0x20                        ;  ref1p_pfm_disqualify        
X , 0x0584  , 0x01                        ;  ref_mb_sem                  
W , 20000 

X , 0x0582  , 0x00                        ;  ref_mb_mask                 
X , 0x0583  , 0x08                        ;  ref_mb_mask                 
X , 0x0584  , 0x02                        ;  ref_mb_sem                  
W , 20000 
X , 0x0585  , 0x61                        ;  ref1n_freq_base             
X , 0x0586  , 0xA8                        ;  ref1n_freq_base             
X , 0x0587  , 0x03                        ;  ref1n_freq_mult             
X , 0x0588  , 0xE8                        ;  ref1n_freq_mult             
X , 0x0598  , 0xCB                        ;  ref1n_pfm_disqualify        
X , 0x0599  , 0x20                        ;  ref1n_pfm_disqualify        
X , 0x0584  , 0x01                        ;  ref_mb_sem                  
W , 20000 

X , 0x0582  , 0x00                        ;  ref_mb_mask                 
X , 0x0583  , 0x10                        ;  ref_mb_mask                 
X , 0x0584  , 0x02                        ;  ref_mb_sem                  
W , 20000 
X , 0x0598  , 0xCB                        ;  ref2p_pfm_disqualify        
X , 0x0599  , 0x20                        ;  ref2p_pfm_disqualify        
X , 0x0584  , 0x01                        ;  ref_mb_sem                  
W , 20000 

X , 0x0582  , 0x00                        ;  ref_mb_mask                 
X , 0x0583  , 0x20                        ;  ref_mb_mask                 
X , 0x0584  , 0x02                        ;  ref_mb_sem                  
W , 20000 
X , 0x0598  , 0xCB                        ;  ref2n_pfm_disqualify        
X , 0x0599  , 0x20                        ;  ref2n_pfm_disqualify        
X , 0x0584  , 0x01                        ;  ref_mb_sem                  
W , 20000 

X , 0x0582  , 0x00                        ;  ref_mb_mask                 
X , 0x0583  , 0x40                        ;  ref_mb_mask                 
X , 0x0584  , 0x02                        ;  ref_mb_sem                  
W , 20000 
X , 0x0598  , 0xCB                        ;  ref3p_pfm_disqualify        
X , 0x0599  , 0x20                        ;  ref3p_pfm_disqualify        
X , 0x0584  , 0x01                        ;  ref_mb_sem                  
W , 20000 

X , 0x0582  , 0x00                        ;  ref_mb_mask                 
X , 0x0583  , 0x80                        ;  ref_mb_mask                 
X , 0x0584  , 0x02                        ;  ref_mb_sem                  
W , 20000 
X , 0x0598  , 0xCB                        ;  ref3n_pfm_disqualify        
X , 0x0599  , 0x20                        ;  ref3n_pfm_disqualify        
X , 0x0584  , 0x01                        ;  ref_mb_sem                  
W , 20000 

X , 0x0582  , 0x01                        ;  ref_mb_mask                 
X , 0x0583  , 0x00                        ;  ref_mb_mask                 
X , 0x0584  , 0x02                        ;  ref_mb_sem                  
W , 20000 
X , 0x0598  , 0xCB                        ;  ref4p_pfm_disqualify        
X , 0x0599  , 0x20                        ;  ref4p_pfm_disqualify        
X , 0x0584  , 0x01                        ;  ref_mb_sem                  
W , 20000 

X , 0x0582  , 0x02                        ;  ref_mb_mask                 
X , 0x0583  , 0x00                        ;  ref_mb_mask                 
X , 0x0584  , 0x02                        ;  ref_mb_sem                  
W , 20000 
X , 0x0598  , 0xCB                        ;  ref4n_pfm_disqualify        
X , 0x0599  , 0x20                        ;  ref4n_pfm_disqualify        
X , 0x0584  , 0x01                        ;  ref_mb_sem                  
W , 20000 

X , 0x0602  , 0x00                        ;  dpll_mb_mask                
X , 0x0603  , 0x01                        ;  dpll_mb_mask                
X , 0x0604  , 0x02                        ;  dpll_mb_sem                 
W , 20000 
X , 0x0606  , 0xA4                        ;  dpll0_bw_var                
X , 0x060E  , 0x0F                        ;  dpll0_range                 
X , 0x060F  , 0xA0                        ;  dpll0_range                 
X , 0x0610  , 0x1F                        ;  dpll0_ref_sw_mask           
X , 0x0611  , 0x1F                        ;  dpll0_ref_ho_mask           
X , 0x0613  , 0x01                        ;  dpll0_etod_ho_mask          
X , 0x0614  , 0xFF                        ;  dpll0_ref_prio_0            
X , 0x061C  , 0x04                        ;  dpll0_ho_filter             
X , 0x061D  , 0x6A                        ;  dpll0_ho_delay              
X , 0x0620  , 0x00                        ;  dpll0_fast_lock_ctrl        
X , 0x0630  , 0x01                        ;  dpll0_phase_bad             
X , 0x0631  , 0x31                        ;  dpll0_phase_bad             
X , 0x0632  , 0x2D                        ;  dpll0_phase_bad             
X , 0x0633  , 0x00                        ;  dpll0_phase_bad             
X , 0x0634  , 0x00                        ;  dpll0_phase_good            
X , 0x0635  , 0x98                        ;  dpll0_phase_good            
X , 0x0636  , 0x96                        ;  dpll0_phase_good            
X , 0x0637  , 0x80                        ;  dpll0_phase_good            
X , 0x0638  , 0x00                        ;  dpll0_duration_good         
X , 0x0604  , 0x01                        ;  dpll_mb_sem                 
W , 20000 

X , 0x0602  , 0x00                        ;  dpll_mb_mask                
X , 0x0603  , 0x02                        ;  dpll_mb_mask                
X , 0x0604  , 0x02                        ;  dpll_mb_sem                 
W , 20000 
X , 0x0606  , 0xA4                        ;  dpll1_bw_var                
X , 0x060E  , 0x0F                        ;  dpll1_range                 
X , 0x060F  , 0xA0                        ;  dpll1_range                 
X , 0x0610  , 0x1F                        ;  dpll1_ref_sw_mask           
X , 0x0611  , 0x1F                        ;  dpll1_ref_ho_mask           
X , 0x0613  , 0x02                        ;  dpll1_etod_ho_mask          
X , 0x0614  , 0xFF                        ;  dpll1_ref_prio_0            
X , 0x061C  , 0x04                        ;  dpll1_ho_filter             
X , 0x061D  , 0x6A                        ;  dpll1_ho_delay              
X , 0x0620  , 0x00                        ;  dpll1_fast_lock_ctrl        
X , 0x0630  , 0x01                        ;  dpll1_phase_bad             
X , 0x0631  , 0x31                        ;  dpll1_phase_bad             
X , 0x0632  , 0x2D                        ;  dpll1_phase_bad             
X , 0x0633  , 0x00                        ;  dpll1_phase_bad             
X , 0x0634  , 0x00                        ;  dpll1_phase_good            
X , 0x0635  , 0x98                        ;  dpll1_phase_good            
X , 0x0636  , 0x96                        ;  dpll1_phase_good            
X , 0x0637  , 0x80                        ;  dpll1_phase_good            
X , 0x0638  , 0x00                        ;  dpll1_duration_good         
X , 0x0604  , 0x01                        ;  dpll_mb_sem                 
W , 20000 

X , 0x0602  , 0x00                        ;  dpll_mb_mask                
X , 0x0603  , 0x04                        ;  dpll_mb_mask                
X , 0x0604  , 0x02                        ;  dpll_mb_sem                 
W , 20000 
X , 0x0606  , 0x96                        ;  dpll2_bw_var                
X , 0x060E  , 0x0F                        ;  dpll2_range                 
X , 0x060F  , 0xA0                        ;  dpll2_range                 
X , 0x0610  , 0x1F                        ;  dpll2_ref_sw_mask           
X , 0x0611  , 0x1F                        ;  dpll2_ref_ho_mask           
X , 0x0613  , 0x02                        ;  dpll2_etod_ho_mask          
X , 0x0614  , 0xFF                        ;  dpll2_ref_prio_0            
X , 0x061C  , 0x04                        ;  dpll2_ho_filter             
X , 0x061D  , 0x6A                        ;  dpll2_ho_delay              
X , 0x0620  , 0x00                        ;  dpll2_fast_lock_ctrl        
X , 0x0630  , 0x01                        ;  dpll2_phase_bad             
X , 0x0631  , 0x31                        ;  dpll2_phase_bad             
X , 0x0632  , 0x2D                        ;  dpll2_phase_bad             
X , 0x0633  , 0x00                        ;  dpll2_phase_bad             
X , 0x0634  , 0x00                        ;  dpll2_phase_good            
X , 0x0635  , 0x98                        ;  dpll2_phase_good            
X , 0x0636  , 0x96                        ;  dpll2_phase_good            
X , 0x0637  , 0x80                        ;  dpll2_phase_good            
X , 0x0638  , 0x00                        ;  dpll2_duration_good         
X , 0x0604  , 0x01                        ;  dpll_mb_sem                 
W , 20000 

X , 0x0602  , 0x00                        ;  dpll_mb_mask                
X , 0x0603  , 0x08                        ;  dpll_mb_mask                
X , 0x0604  , 0x02                        ;  dpll_mb_sem                 
W , 20000 
X , 0x0606  , 0x96                        ;  dpll3_bw_var                
X , 0x0610  , 0x1F                        ;  dpll3_ref_sw_mask           
X , 0x0611  , 0x1F                        ;  dpll3_ref_ho_mask           
X , 0x0614  , 0xF0                        ;  dpll3_ref_prio_0            
X , 0x0615  , 0xFF                        ;  dpll3_ref_prio_1            
X , 0x0616  , 0xFF                        ;  dpll3_ref_prio_2            
X , 0x0617  , 0xFF                        ;  dpll3_ref_prio_3            
X , 0x0618  , 0xFF                        ;  dpll3_ref_prio_4            
X , 0x061C  , 0x04                        ;  dpll3_ho_filter             
X , 0x061D  , 0x6A                        ;  dpll3_ho_delay              
X , 0x0604  , 0x01                        ;  dpll_mb_sem                 
W , 20000 

X , 0x000B  , 0x18                        ;  central_freq_offset         
X , 0x000C  , 0x00                        ;  central_freq_offset         
X , 0x000D  , 0x72                        ;  central_freq_offset         
X , 0x000E  , 0xB0                        ;  central_freq_offset         
W , 100000 
X , 0x0088  , 0x12                        ;  gpio_select_0               
X , 0x0089  , 0x18                        ;  gpio_select_0               
X , 0x008A  , 0x03                        ;  gpio_config_0               
X , 0x008B  , 0x04                        ;  gpio_select_1               
X , 0x008C  , 0x4C                        ;  gpio_select_1               
X , 0x008D  , 0x02                        ;  gpio_config_1               
X , 0x008E  , 0x12                        ;  gpio_select_2               
X , 0x008F  , 0x19                        ;  gpio_select_2               
X , 0x0090  , 0x03                        ;  gpio_config_2               
X , 0x0211  , 0x02                        ;  dpll_ctrl_0                 
X , 0x0215  , 0x02                        ;  dpll_ctrl_1                 
X , 0x0219  , 0x02                        ;  dpll_ctrl_2                 
X , 0x021D  , 0x03                        ;  dpll_ctrl_3                 
X , 0x024D  , 0x01                        ;  gp_squelch_mask             
X , 0x0400  , 0x01                        ;  gp_ctrl                     
X , 0x0404  , 0x61                        ;  gp_freq_base                
X , 0x0405  , 0xA8                        ;  gp_freq_base                
X , 0x0406  , 0x00                        ;  gp_freq_mult                
X , 0x0407  , 0x75                        ;  gp_freq_mult                
X , 0x0408  , 0x30                        ;  gp_freq_mult                
X , 0x0422  , 0x00                        ;  gp_out_div_0                
X , 0x0423  , 0x00                        ;  gp_out_div_0                
X , 0x0424  , 0x00                        ;  gp_out_div_0                
X , 0x0425  , 0x1E                        ;  gp_out_div_0                
X , 0x0432  , 0x00                        ;  gp_out_div_1                
X , 0x0433  , 0x00                        ;  gp_out_div_1                
X , 0x0434  , 0x00                        ;  gp_out_div_1                
X , 0x0435  , 0x1E                        ;  gp_out_div_1                
X , 0x0450  , 0x01                        ;  gp_out_en                   
X , 0x04B4  , 0xF4                        ;  hp_freq_base_2              
X , 0x04B5  , 0x24                        ;  hp_freq_base_2              
X , 0x04B6  , 0x00                        ;  hp_freq_base_2              
X , 0x04B7  , 0x00                        ;  hp_freq_base_2              
X , 0x04C0  , 0x08                        ;  hp_hsdiv_2                  
X , 0x04E0  , 0x11                        ;  hp_out_en                   
X , 0x04E1  , 0xA0                        ;  hp_out_mux                  
X , 0x0500  , 0x19                        ;  hp_out_msdiv_0              
X , 0x0505  , 0x05                        ;  hp_out_ctrl_0               
X , 0x050B  , 0x40                        ;  hp_out_stop_0               
X , 0x0510  , 0x01                        ;  hp_out_msdiv_1              
X , 0x0540  , 0x7D                        ;  hp_out_msdiv_4              
X , 0x0541  , 0x00                        ;  hp_out_lsdiv_4              
X , 0x0542  , 0x00                        ;  hp_out_lsdiv_4              
X , 0x0543  , 0x00                        ;  hp_out_lsdiv_4              
X , 0x0544  , 0x02                        ;  hp_out_lsdiv_4              
X , 0x0545  , 0x05                        ;  hp_out_ctrl_4               
X , 0x0548  , 0x10                        ;  hp_out_lsctrl_4             
X , 0x0480  , 0x11                        ;  hp_ctrl_1                   
X , 0x04B0  , 0x21                        ;  hp_ctrl_2                   
X , 0x04E8  , 0x01                        ;  group register

W , 2000000 
X , 0x0210  , 0x03                        ;  dpll_mode_refsel_0          
X , 0x0214  , 0x03                        ;  dpll_mode_refsel_1          
X , 0x0218  , 0x03                        ;  dpll_mode_refsel_2          
X , 0x021C  , 0x03                        ;  dpll_mode_refsel_3          

; Register Configuration End
; Register Write Count = 221

;======================================================================
