The DCB/xxxSC series of Dialogic audio conferencing products can provide from 32 to 96 conferencing resources in increments of 32. The number of resources on any board is determined by the number of DSPs resident on the board. The baseboard with one DSP, DCB/320SC, is used for a 32 conferencing resource solution. The baseboard with two DSPs, DCB/640SC, is used for a 64 conferencing resource solution. The baseboard and daughterboard with an additional DSP, DCB/960SC, is used for a 96 conferencing resource solution.
Each DCB/SC product is built of one or more conference subassemblies. A subassembly consists of an SC2000 chip and a Motorola 56002 DSP (with attendant high speed RAM). Both of these components are under the control of the single Intel 80C286 control processor, and serviced by a single High-level Data Link Controller (HDLC) HDLC controller and dual-ported shared RAM.
Each conference subassembly can fully process up to 32 digitally derived conference parties. The subassembly is capable of maintaining up to 16 simultaneous conferences. The maximum conference size is 32 parties, hence all 32 parties of a given subassembly could reside in the same conference. Conferences can be created, deleted, or modified up to the conferee limits. Each subassembly implements the DCB/SC conferencing features described in Section 1.2.
The on-board control processors control access to the SCbus. This message bus is a separate SCbus channel carrying messages and control information among devices, such as out-of-band signaling and collision detection and resolution information. Out-of-band signaling enables faster response time to the messages and control information carried on the dedicated message channel. Bus contention and resolution capability uses a set of fixed and rotating guidelines to detect when two devices are trying to access the same SCbus slot and resolves this situation so each resource has equal access.
The on-board control processor(s) control all operations of the DCB/SC board via a local bus and interprets and executes commands from the host PC. The processor(s) handle real-time events, manages data flow to the host PC to provide faster system response time, reduces PC host processing demands, and frees the DSPs to perform signal processing. Communications between a processor and the host PC is via the dual-port shared RAM that acts as an input/output buffer. This RAM interfaces to the host PC via the ISA bus. All operations are interrupt driven to meet the demands of real-time systems. When the system is initialized, DCB/SC firmware to control all board operations is downloaded from the host PC to the on-board code/data RAM and DSP RAM.
The board locator technology (BLT) circuit operates in conjunction with a rotary switch eliminating the need to set any jumpers or DIP switches.
Figure 1. Overview of the DCB/320SC Board
Figure 2. Overview of the DCB/640SC Board
Figure 3. Overview of the DCB/960SC Board
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