An E-1 circuit is a digital two-way connection operating at a speed of 2.048 Mbps. This rate is achieved by combining 32 time slots operating at a rate of 64 Kbps.
64,000 bps (Individual Voice Channel Rate)
x 32 (Number of Channels or Time Slots)
2,048,000 (E-1 Circuit Rate)
These 32 time slots include 30 time slots available for up to 30 voice channels, one time slot dedicated to carrying frame synchronization information (time slot 0), and one time slot dedicated to carrying signaling information (time slot 16). The E-1 compatible digital network interface boards de-multiplex the 30 voice channels and pass them on to E-1 compatible resource modules.
3.2.1. E-1 Frame FormatOn an E-1 circuit, data is organized into frames on a byte-interleaved basis. Data is taken from each voice channel a byte at a time. The resulting E-1 frame contains 32 time slots: one to carry frame synchronization information, one to carry signaling information, and 30 to carry voice channel data. Each time slot contains 8 bits, for a total of 256 bits per frame. Figure 3 illustrates the structure of an E-1 frame.
Figure 3. E-1 Frame Format
E-1 frame format numbers time slots from 0 to 31.
E-1 frames 0 through 15 are combined into one multiframe. Figure 4 illustrates the structure of an E-1 multiframe.
Figure 4. E-1 Multiframe Format
3.2.2. E-1 SynchronizationTime slot 0 of each frame (frames 0 through 15 of a multiframe) carries the information needed to identify voice channels for the receiver on E-1 systems. The pattern carried by time slot 0 alternates between two patterns: the first is a 7-bit pattern (0011011) in bit positions 6 through 0 and the second is a pattern of national and international bits with a single 1-bit in bit position 6. Figure 5 shows the alternating bit patterns in odd and even frames.
Figure 5. Individual Frame Synchronization
See Section 3.2.4. E-1 National and International Bits for an explanation of the E-1 national and international bits pictured in Figure 5.
Frame 0 (the first frame within an E-1 multiframe) contains additional synchronization information to identify the beginning of a multiframe. The beginning is identified by a pattern of four zeros in bit positions 7 through 4 of time slot 16, frame 0. Figure 6 illustrates the bit pattern found in time slot 16 of frame 0.
Figure 6. Multiframe Synchronization
If these frame or multiframe bit patterns cannot be found, the resulting error is known as a Frame Sync Error (FSERR) or Multiframe Sync Error (MFSERR). If either an FSERR or MFSERR error is detected, a remote alarm or a distant multi-frame alarm is sent to the remote end. The condition exists until synchronization is recovered. See Section 3.3.2. Loss of Synchronization Alarm Handling for information on E-1 alarm handling.
3.2.3. E-1 SignalingThe Conference of European Postal and Telecommunications administrations (CEPT) defines how bits of a PCM carrier system in E-1 areas will be used and in what sequence. E-1 circuits use the Channel Associated Signaling (CAS) protocol. Frames using CAS share time slot 16, which carries signaling information for two time slots or voice channels at a time.
Time slot 16 contains two groups of four bits, known as nibbles, that are designated the upper nibble and the lower nibble. Two channels send their signaling bits in each frame - one using the upper nibble, the other using the lower nibble. As explained in Section 3.2.1. E-1 Frame Format on E-1 frame format, it takes 15 frames to carry signaling information for each of the 30 voice channels.
Time slot 16 of frame 0 carries a special pattern. The upper nibble carries a pattern of four 0s, which identifies the frame as frame 0 of an E-1 multiframe.
The lower nibble of time slot 16 in frame 0 carries a pattern of extra bits and an alarm bit. The X bits pictured in Figure 7 are the extra bits used for multiframe synchronization (see Section 3.2.2. E-1 Synchronization). The Y bit pictured in Figure 7 is the distant multiframe alarm bit (see Section 3.3.2. Loss of Synchronization Alarm Handling).
Time slot 16 of frame 1 in an E-1 multiframe carries signaling information for the first and 16th channels. Time slot 16 of frame 2 in an E-1 multiframe carries signaling information for the 2nd and the 17th channels. This continues until frame 15 which carries signaling information for the 15th and 30th channels.
Figure 7. Channel Associated Signaling (CAS) Protocol
Caution
Do not set signaling bits ABCD to 0000. As explained in Section 3.2.2. E-1 Synchronization on E-1 synchronization, this setting is used to identify frame 0 of an E-1 multiframe.
Clear Channel TS16 FeatureThe Clear Channel TS16 feature allows the use of time slot 16 for data on E-1 interface boards. This feature is enabled or disabled by adding one of the following lines to /usr/dialogic/cfg/dialogic.cfg:
FEATURES = TS16_CLEAR
This command selects Clear Channel Time Slot 16 (CCTS16) for E-1 interface boards, ignores E-1 signaling received from the network on time slot 16, and transmits FFH. Access to time slot 16 is not available.
FEATURES = TS16_SIG
This command specifies that the E-1 interface board will use the default of E-1 signaling on time slot 16.
3.2.4. E-1 National and International BitsNational and international bits are set in time slot 0. The most significant bit (bit position 7) in time slot 0 of each frame contains the international bit. The national bits occupy bit positions 0 through 4 of time slot 0 of every second frame. Figure 8 shows national and international bit settings.
Figure 8. E-1 National and International Bits
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