2.10. Clock Master Fallback List

The Primary Clock Master provides bus timing (bit clock and frame synchronization) to all boards in the system. The Primary Clock Master derives its timing from either a network interface (optimum) or from its own internal oscillator. When clocking is derived from a network interface, the Primary Master Clock uses the CT Bus NETREF signal as the clock reference (see Figure 2, CT Bus Clocking).

Under normal operation, the Primary Clock Master clock output is re-driven by the Secondary Clock Master, providing redundant backup clocking to all boards in the system should the Primary Clock Master fail.

Figure 2. CT Bus Clocking

In addition, multiple clock master fallback devices can be defined using the clock master fallback list. The clock master fallback list defines a list of master capable devices in a preferred order. If the current Primary Clock Master should fail, this list is consulted by the system and a new Primary Clock Master is assigned.

The CT Bus includes a primary clock signal line (Line A) and a secondary clock signal line (Line B). Either Line A or Line B can be assigned as the Primary Line (driven by the Primary Clock Master). The remaining line is assigned as the Secondary Line (driven by the Secondary Clock Master). The Primary Line carries clock synchronization to all boards in the system.

Primary and Secondary Clock Masters are always selected automatically by the system. When a clock failure occurs and the clock master fallback list is defined, the list is consulted by the system (without the intervention of the administrative application) to determine the new clock master device. The list is consulted from the first entry down each time to assign the best clock master device available.

If the clock master fallback list is not defined, the system will select a new clock master device on its own, should a failure occur.

For example, if the clock fallback list is defined as follows:

1. Board 1
2. Board 2
3. Board 5
4. Board 4

and Board 2 is the current Primary Clock Master, if a failure should occur on the Primary lines, the system will first check if Board 1 is capable of being the Primary Clock Master before proceeding further down the list.

If a previously failed clock master recovers, the system will not automatically assign that clock master as the Primary Clock Master.

The clock fallback list is defined using the NCM_SetClockMasterFallbackList( ) function. Clock fallback clock master sources are defined with the NCM_SetTDMBusValue( ) function.

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