2.1.5. Understanding the CT Bus

The Enterprise Computer Telephony Forum (ECTF) standard H.100/H.110 CT Bus provides a fault-tolerant hardware interface for H.100 PCI and H.110 cPCI telephony hardware devices (boards). Features include redundant clocking (H.100 and H.110) and the ability to stop, start, and remove individual boards without interrupting the operation of other boards sharing the bus (H.110 only).

This section covers the following topics:

• H.100/H.110 Bus Concepts
• Default Configuration
• Fault Recovery
• H.100/H.110 Bus Features
• Restrictions and Limitations

H.100/H.110 Bus Concepts

A number of concepts and definitions, especially regarding clocking, are central to understanding the H.100/H.110 CT Bus. Figure 1 illustrates the CT Bus clocking concepts.

Figure 1. CT Bus Clocking

• Clock Master(s): A Clock Master is a board that provides timing for all other boards connected to the bus. The H.100/H.110 Bus has two types of Clock Masters: Primary Clock Master and Secondary Clock Master.
  • Primary Clock Master: The Primary Clock Master drives bit and framing clocks onto one of two pairs of (primary) lines of the CT Bus. The Primary Clock Master can provide clocking derived from either a network interface (recommended) or from its internal oscillator. When clocking is derived from the network, the Primary Clock Master synchronizes its output to the CT Bus CT_NETREF signal (NETREF).
  • Secondary Clock Master: Under normal conditions, the Primary Clock Master's output is redriven on a second (secondary) pair of lines by the Secondary Clock Master, providing a redundant backup set of clocks for all boards in the system if the Primary Clock Master fails.
• Line A, Line B: Line A and Line B are the two pairs of lines that the H.100/H.110 CT Bus sets aside for clock synchronization. Either Line A or Line B can be assigned as the Primary Line; the remaining line is assigned as the Secondary Line. The Primary Line is driven by the Primary Clock Master and the Secondary Line is driven by the Secondary Clock Master.
• Slave: All boards that are not Clock Masters are defined as (CT Bus) slaves. Slaves normally derive their timing from the Primary Line but will switch to the Secondary Line if the integrity of the signals on the Primary Line degrades.
• NETREF FRU: The NETREF FRU (field replaceable unit), also known as the Network Reference, is a board that is used to drive a reference clock onto the CT Bus. The system's Primary Clock Master board normally uses the NETREF FRU's output (CT_NETREF signal) as its input reference. (The Secondary Clock Master is normally configured to use CT_NETREF as its reference only during a primary failure situation.) Note that H.100 uses one NETREF FRU. For H.110, there may be two NETREF FRUs in the system. Any digital network interface to the NETREF FRU can be used to generate the NETREF signal. The current implementation provides NETREF operation at 8 kHz.
• CT_NETREF: The CT_NETREF signal carries a network clock signal that may be used by the Primary Clock Master and Secondary Clock Master as their reference. The NETREF FRU is the board that drives the reference signal CT_NETREF. The H.100 version of the CT Bus uses one CT_NETREF signal, while the H.110 version uses two independent CT_NETREF signals (_1 and _2).
• Holdover Clock: The Holdover Clock emulates the NETREF reference signal used as a reference by the Primary Clock Master to provide clocking to the bus. If the NETREF reference signal fails, the H.100/H.110 CT Bus Holdover Clock takes over as the temporary reference signal provider until a new reference is connected. The Holdover Clock is ideally engaged only for as long as it takes to switch to a different reference signal, although it can operate indefinitely with minimal degradation in bus performance. In the current implementation, failure of a network interface on the NETREF FRU is not detected as a reference signal failure.
• Compatibility Clocks: The Compatibility Clocks are a feature of the H.100/H.110 CT Bus that enables H.100/H.110 boards to interoperate with SCbus boards in the same system.

  Note: The current implementation gives you the option to operate the system in pure SCbus mode. However, when used in SCbus mode, the Intel® Dialogic® System Software does not support the fault recovery features discussed in this section, such as Primary Clock Master and Secondary Clock Master and NETREF.

• Group One Through Five: The data streams in the H.100/H.110 CT Bus are divided into two sets of 16 streams. The first (lower) set of 16 data streams is comprised of four groups of four streams. The second (upper) set of 16 data streams comprises group 5. The current implementation limits all groups of the lower set (1-4) to run at the same clock speed:
  • 8 MHz (for H.110 CT Bus only), or
  • 4 MHz (for H.100 CT Bus interoperability with SCbus products, or for SCbus mode only)

Default Configuration

When the Intel Dialogic System is initiated, it performs a number of configuration tasks to set up an operating H.100 or H.110 Bus. This process includes the following tasks:

• One board is designated as the Primary Clock Master driving the Primary Line from its internal oscillator.
• Another board is designated as the Secondary Clock Master driving the Secondary Line from its internal oscillator.
• All boards on the bus, including the Primary Clock Master and Secondary Clock Master, derive timing from the Primary Line.
• The TDM Bus Type is set to H.100 or H.110, and the group clock rates are all set at 8 MHz. (If SCbus products are present, then the default clock rate is 4 MHz.)

It is recommended that you derive clocking from a digital network trunk, if available, rather than the board's internal oscillator. For further details, see Section 4.4, Designating the Clock Source.

Fault Recovery

Failure of the Primary Clock Master or NETREF FRU is handled in the following ways:

• Failure of Primary Clock Master: If the Primary Clock Master fails, the boards listening to the Primary Line detect the failure and automatically switch to the Secondary Line, at which point the Secondary Clock Master becomes the Primary Clock Master. At this time, a new Secondary Clock Master is selected automatically if another board is available. (If the board that served as Primary Clock Master comes back online, it is not automatically designated again as the Primary Clock Master.)
• Failure of network interface driving NETREF: If the NETREF FRU detects failure of the network interface driving NETREF, it switches to derive the NETREF signal from an internal oscillator. In the current implementation, the network interface failure does not result in the engagement of the Holdover Clock.

Most of the steps that occur when setting up and recovering the H.100/H.110 CT Bus clocking scheme can be carried out explicitly by the user or automatically by the Intel Dialogic System Software. For example, the system automatically selects a Primary Clock Master, but this choice can be overridden by the user by changing the Primary Master FRU parameter in the Intel Dialogic Configuration Manager (DCM). For more information, see Section 4.4, Designating the Clock Source.

H.100/H.110 Bus Features

The current implementation supports the following H.100/H.110 CT Bus features:

• Automatic assignment of Primary Clock Master and Secondary Clock Master
• Bus mode support for:
  • H.100 (for PCI form factor)
  • H.110 (for cPCI form factor)
  • SCbus compatibility of H.100/H.110 running at 4 MHz
  • Pure SCbus
• Starting and stopping the Intel Dialogic System and individual boards locally through DCM and remotely through DCM or BoardWatch version 2.0
• Modification of all H.100/H.110 CT Bus configuration parameters through the DCM GUI
• Configuration of both Springware SCbus boards and DM3 PCI/cPCI boards in the same bus
• Starting, stopping, and removing a single H.110 board
• Automatic reassignment to Secondary Clock Master when Primary Clock Master is stopped
• Removing stopped CompactPCI boards from the bus with no effect on other running boards (for more information, refer to Section 5.6.2, Replacing CompactPCI Boards).

Restrictions and Limitations

The current implementation is subject to the following restrictions and limitations with respect to the H.100/H.110 CT Bus:

• If all the boards in your system are capable of both A-law and m-law, the default encoding method is m-law; E-1 users must explicitly set A-law using the Media Type parameter through DCM. See Section 4.5, Setting the Encoding Method for DM3 E-1 Applications.
• Each physical chassis can support only one physical TDM bus.
• When a stopped board is removed and replaced, it must be replaced with an identical model, which must be inserted into the same slot.
• Notification of Intel Dialogic System Software errors is generally limited to an indication that one or more errors occurred; additional information can be retrieved from the Windows Event Viewer.
• If any single board in the system is run in SCbus mode, then all boards in the system must run in SCbus mode as well.
• To derive clocking from an SCbus board, the entire system must be in SCbus mode (see Section 4.4, Designating the Clock Source).
• The network interface from which the NETREF FRU derives clocking must be selected by the user (the default clock source is the Primary Clock Master's internal oscillator).

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