2.4.  Functional Description of an SCX160 SCxbus Adapter

• 2.4.1.  FIFO Elastic Buffers
• 2.4.2.  SCxbus Interface
• 2.4.3.  On-Board Control Processor
• 2.4.4.  Synchronization Circuitry
• 2.4.5.  Board Locator Technology Circuit

Time slots on the SCbus and SCxbus are transmitted in bundles of 64 across each of 16 lines for a total of 1024 time slots/bus. Each bundle of time slots is handled as a data stream by the SCX160 SCxbus Adapter. Each of these 16 data streams is interfaced to the SCX160 SCxbus Adapter by one of 16 data transceivers (a driver and receiver pair). Therefore, each transceiver handles 64 time slots.

As shown in Figure 3, SCbus data stream 0 outbound (DS0 OUT) comprising time slots 0 to 63, enters the SCX160 SCxbus Adapter via receiver 1A. All interface receivers are permanently enabled. DS0 OUT is then applied to an SCxbus FIFO (First-In, First-Out) elastic buffer and then via an SCxbus interface driver 1B to the SCxbus.

Data streams transmitted across the SCxbus are handled in a similar fashion. As shown in Figure 3, SCxbus data stream 1 inbound (DS1 IN) comprising time slots 64 to 127, enters the SCX160 SCxbus Adapter via receiver 2B. These interface receivers are also permanently enabled. DS1 IN is then applied to an SCbus FIFO elastic buffer and then via an SCbus interface driver 2A to the SCbus.

2.4.1.  FIFO Elastic Buffers

The SCbus and SCxbus FIFO elastic buffers minimize any impact due to slip by controlling frame slip when a node uses independent clock. These buffers provide elasticity by absorbing clock drift so that slip is restricted to one PCM (Pulse Code Modulated) frame added or dropped. The FIFO buffer design incorporates dual-port zero fall-through time, asynchronous or coincident read and write clocks, and a FIFO depth of two PCM frames. A FIFO control circuit locks both the read and write clocks of the FIFO elastic buffers in both phase and frequency (synchronous operation) to their respective bus.

Figure 3.  SCX160 SCxbus Adapter Functional Block Diagram

If a FIFO elastic buffer fills, normal operation continues after the start of the next frame. During this frame all writes are inhibited, thus bringing the FIFO elastic buffer to about half full and one full frame is thrown away (positive slip). The FIFO elastic buffer is now about half full and normal operations are resumed.

If a FIFO elastic buffer empties, a full frame of data is repeated (negative slip) to bring the buffer back to about half full.

Each FIFO elastic buffer is continuously tested by inserting an on-board generated test pattern in unused data stream 17 and checking the test pattern at the output of the FIFO elastic buffer.

2.4.2.  SCxbus Interface

In addition to the transceivers, the SCxbus interface comprises SCSI-3 compliant receiver fail-safe circuits, EMI protection, term power and a 68-pin female connector mounted on the module's faceplate. A regulated +5 VDC is provided to the TERMPWR pin of the SCxbus connector for power sharing among all active SCX160 SCxbus Adapters connected to the SCxbus.

2.4.3.  On-Board Control Processor

An on-board 80C186 Control Processor manages all operations of the SCX160 SCxbus Adapter via an on-board bus and interprets and executes commands from the host PC. This microprocessor handles real-time events, communications and interrupts with the host PC to provide faster system response time. Communications between this Control Processor and the host PC are via the dual port shared RAM that acts as an input/output buffer. This RAM interfaces to the host PC via the AT (ISA) bus. All operations are interrupt driven to meet the demands of real-time systems. When the node is initialized, firmware to control all board operations is downloaded from the host PC to the on-board code/data RAM. This downloadable firmware gives the board all of its intelligence and enables easy feature enhancement and upgrades.

2.4.4.  Synchronization Circuitry

The synchronization circuitry comprises a Crystal Oscillator, a PLL Clock and Clock Fallback Control Logic circuits. The Crystal Oscillator provides a local clock source with a _20 ppm stability to be used as a reference frequency in the event of a clock reference failure.

The PLL Clock maintains clock synchronization and frame synchronization (frame alignment) using one of the following as the reference clock source:

• Right SCxbus clock
• Left SCxbus clock
• 8 kHz external reference clock from the SCxbus
• SCbus clock
• Local Crystal Oscillator (default)

The on-board Control Processor generates the control signals that select the appropriate reference clock source. An alarm event is generated if an error is detected in any clock.

At Dialogic Service startup, one node must be designated as the SCxbus master clock node. This node drives the Right SCxbus clock line. Other boards in this node, including the SCX160 SCxbus Adapter, can be designated as SCxbus fallback masters for the SCbus master clock. The SCbus master clock should be designated as the clock reference to be used by the SCX160 SCxbus Adapter to synchronize clock sent over the Right SCxbus clock line.

Another node should be designated as the SCxbus fallback master clock node. This node phase locks to the Right SCxbus clock and drives the Left SCxbus clock line. The SCX160 SCxbus Adapter in all other nodes synchronize to the Right SCxbus clock. Typically, a network module in this node is designated to provide SCbus master clock.

NOTE:

For more on clock designations, see Chapter 4.  Clocking.

A clockfail signal from the SCbus in the master clock node indicates the status of the SCbus master clock source. If this clock fails, then the SCxbus master clock node stops driving the Right SCxbus clock line if the Left SCxbus clock is present. When the other nodes in the system detect loss of Right SCxbus clock, they automatically switch their clock synchronization to the Left SCxbus clock. The SCxbus fallback master clock node continues to drive the Left SCxbus clock independent of the Right SCxbus clock.

Right and Left Frame Synchronization signals are also supported on the SCxbus and are in phase synchronization. A Frame Synchronization signal is also available from the SCbus. These Frame Synchronization signals are used by the system clock circuits and the FIFO Control circuits.

The 8 kHz external reference clock can be used as an independent clock source. Typically, this clock is a composite station clock as seen in a CO (Central Office) environment.

2.4.5.  Board Locator Technology Circuit

The Board Locator Technology circuit operates in conjunction with a rotary switch to determine and set Shared RAM memory base address in the host PC and non-conflicting slot (board identification number from 0 to 31) and IRQ interrupt-level parameters. This feature eliminates the need to set jumpers or DIP switches. A board locating sequence can locate each SCX160 SCxbus Adapter in the system and assign each to a unique address in the host PC or to the same base address. If the SCX160 SCxbus Adapter detects a board enable sequence that does not match its board identification, the SCX160 SCxbus Adapter automatically disables its Shared RAM. This feature allows the host PC to enable a specific SCX160 SCxbus Adapter for host PC communications without having to disable previously enabled boards.

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