2.6.  Test Access Logic

The Test Access Logic circuits perform the following functions:

• Continuously testing for errors in the SCbus and SCxbus data streams at the interface drivers and at the FIFO elastic buffers
• Monitoring the status of the synchronization circuitry

The Test Access Logic circuits compare data transmitted over each SCbus and SCxbus driver line with data echoed on a corresponding receiver line to continuously verify data integrity for each data stream. If different, an error counter is incremented and this count is saved until read and cleared by the Control Processor. In addition, these circuits monitor the status of clock signals and various programming status indicators.

Using the interface circuits as an example, the Test Access Logic connections can be configured as shown in Figure 4. Then data transmissions can be monitored as follows:

• To the SCxbus: DS0 transmissions from the SCbus are transmitted to the SCxbus by SCxbus data transceiverdriver 1B and are also input to receiver 1B. A monitor 1 line inputs the DS0 input of driver 1B (output of the SCxbus FIFO elastic buffer) to the Test Access Logic circuits where it is compared on a bit-by-bit basis with the DS0 data output received via the monitor 2 line from receiver 1B. If different, the error counter is incremented.
• From the SCxbus: DS1 transmissions from the SCxbus are transmitted to the SCbus by SCbus data transceiver driver 2A and also input to receiver 2A. A monitor 3 line inputs the DS1 input to driver 2A to the Test Access Logic circuits where it is compared on a bit-by-bit basis with the DS1 data output received via monitor 4 line from receiver 2A. If different, the error counter is incremented.

The Test Access Logic circuits monitoring capabilities as illustrated above apply to all enabled SCbus and SCxbus data transceivers.

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