4.  Clocking

4.1.  Overview of Clocking

To achieve communication between nodes, each SCX160 SCxbus Adapter interconnects, manages and controls the SCbus and the SCxbus interfaces. The software architecture for the SCX160 SCxbus Adapter incorporates a PLL (Phase Locked Loop) process in the SCX160 SCxbus Adapter's firmware that handles all clocking events and executes the SCbus and the SCxbus clock state changes.

This chapter provides the following information regarding clocking:

• Designating clock modes - information for determining which nodes will provide master and fallback master clock reference for all the other nodes
• Clock synchronization - a description of the various sources that can be used as clock references and of synchronous and plesiochronous clocked systems
• Required clock designations - a summary of clocking mode designations and selections, including examples of synchronous and plesiochronous multi-node systems
• Clock states - a discussion of clock states, clock alarms, and clock state transitions

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