4.3.  Clock Synchronization

• 4.3.1.  Synchronous and Plesiochronous Operation
• 4.3.2.  Clock Fallback

The SCX160 SCxbus Adapters in the system maintain clock synchronization using one of the following as the reference clock source:

• Right SCxbus clock
• Left SCxbus clock
• 8 kHz external reference clock from the SCxbus
• SCbus clock
• Local Crystal Oscillator

The on-board Control Processor generates the control signals that select the appropriate reference clock source. An alarm event is generated if an error is detected in any clock (see Section 4.5.1.  Clock Alarms for more information).

Typically, the SCbus clock is used as the reference clock source for SCX160 SCxbus Adapters in the nodes that have been designated as either the master clock or the fallback master clock. For all other nodes/SCX160 SCxbus Adapters, the SCxbus clock is used as the reference clock source.

For more on clock synchronization, see Section 2.4.4.  Synchronization Circuitry.

4.3.1.  Synchronous and Plesiochronous Operation

An SCX160 SCxbus Adapter multi-node system can operate as either a synchronous or plesiochronous clocked system. In a synchronous system, all nodes other than the Master Clock and Fallback Master Clock nodes operate in SCxbus slave mode. In a plesiochronous system all nodes other than the Master Clock and Fallback Master Clock nodes operate in SCbus slave mode AND in SCxbus slave mode simultaneously. For examples of each of these types of systems, see Section 4.4.1.  Clocking Examples.

4.3.2.  Clock Fallback

The application can change the SCX160 SCxbus Adapter clocking configuration during system operation, especially in the event of multiple failures. This level of clock fallback needs to be incorporated into a Clock Fallback List to be handled by the application or the system administrator.

If the SCbus Master Clock in the SCxbus Master Clock node fails, the next entry on this node's clock fallback list (typically another Network Interface Board) provides SCbus Master Clock. If the SCbus Master Clock falls back to the SCX160 SCxbus Adapter, the SCX160 SCxbus Adapter initiates system clock recovery by looking for the Left SCxbus clock. If detected, the Right SCxbus clock is suppressed to initiate fallback in the other system nodes.

The master clock node then tries to clock from the Left SCxbus clock. If unsuccessful (Left SCxbus clock not present), this node uses its local oscillator as the clock reference and provides both Right SCxbus clock and the SCbus Master Clock signal. If successful, this node provides the local SCbus Master Clock signal.

If an alternate SCxbus Master Clock Node is to be designated by the application or the system administrator, then un-designate the current SCxbus Master Clock Node and designate the new SCxbus Master Clock Node. This newly designated node starts driving the free Right SCxbus Clock and Frame Synchronization line after synchronizing to its designated reference. Once Right SCxbus Clock is detected by the other nodes, they will automatically synchronize to the Right SCxbus Clock, thus completing overall system clock recovery.

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