4.5.  Clock States

• 4.5.1.  Clock Alarms
• 4.5.2.  SCxbus Clock State Machine
• 4.5.3.  SCxbus Clock State Transitions
• SCxbus Master State Clock Node Transitions
• SCxbus Wait Master State Clock Node Transitions
• SCxbus Fallback Master State Clock Node Transitions
• SCxbus Wait Fallback Master State Clock Node Transitions
• 4.5.4.  SCbus Clock State Machine
• 4.5.5.  SCbus Clock State Transitions
• SCbus Master State Clock Node Transitions
• SCbus Wait Master State Clock Node Transitions
• SCbus Fallback Master State Clock Node Transitions

The clock state of each node is initially set to Slave state for the SCxbus. This clock state can be changed in any of the following ways:

• At Dialogic Service startup by adding the SCX160 SCxbus Adapter to the board configuration file
• By the application at any time during system operations by issuing a scx_setbrdparm( ) function
• By an alarm event indicating a clock failure

Clock alarms, clock state machines and clock state transitions are discussed in the following sections.

4.5.1.  Clock Alarms

The PLL (Phase Locked Loop) process gathers all PLL statistics and forwards all PLL alarm conditions to an Alarm process. This Alarm process passes the alarm messages to the host computer in accordance with the alarm masks that have been set. Alarm masks enable or disable the internal alarms. Each internal alarm has its own mask and is mapped to a host alarm event and a host alarm state byte. The default is to disable all alarms.

When a clock failure is detected the following occur:

• A hardware interrupt (maskable) is generated
• A TSCX_ALARM alarm event is generated
• A clock failure timer is started

Every 40 msec, this timer initiates a poll of the clock status. If the failed clock has recovered, then a clock recovered event is posted.

Alarm information is stored in the SCXBP_CLK_HISTORY clock history bitmask parameter (see the scx_getbrdparm( ) function in Chapter 6.  Function Reference for details). The SCXBP_CLK_HISTORY bitmask defines the specific clock event that occurred. This information is retrieved using the scx_getbrdparm( ) function.

See Table 7.  Clock Alarm Events for a list of SCX160 SCxbus Adapter clock alarm events and their corresponding parameter values. A clock failure event may cause a transition to a different clock state.

Table 7.  Clock Alarm Events

Clock Failure Event	SCXBP_CLK_HISTORY Value
Right SCxbus clock	SCXST_SCX_RCLOCK
Left SCxbus clock	SCXST_SCX_LCLOCK
SCbus clock	SCXST_SC_CLOCK
Clockfail signal from SCbus	SCXST_SC_CLOCK_FAIL_SIG
External reference clock from SCxbus	SCXST_EXTCLOCK
PLL out-of-lock	SCXST_PLL_REF

4.5.2.  SCxbus Clock State Machine

The SCxbus clock state machine controls the clocking on the SCxbus interface of the SCX160 SCxbus Adapter and also determines the clock source used for the PLL clock. Its objective is to ensure that the SCxbus always has a clock and to ensure that a clock signal is never erroneously placed on a clocked SCxbus line.

If the clock reference for the master SCxbus clock node fails, the Master clock state at this node automatically changes to the Wait Slave state (see Section 4.5.3.  SCxbus Clock State Transitions) and all nodes automatically start clocking from the SCxbus left clock provided by the Fallback Master node.

NOTE:

The return to the master clocking state at the original master node is either automatic due to recovery of the clock reference or the application must issue an scx_setbrdparm( ) call to designate a new master clock reference.

The SCxbus clock state machine changes from an existing state to a new state in response to a command from the application or an event such as a clock failure. See Table 8.  SCxbus Clock State Transition Events for a summary of the commands and events that can cause a clock state transition in the SCxbus state machine. To retrieve the values listed, use the scx_getbrdparm( ) function.

Table 8.  SCxbus Clock State Transition Events

Parameter Value	Description
SCXCM_MASTER	SCXBP_SCX_CLOCK_MODE parameter designates node to be SCxbus master - i.e., to provide right SCxbus clock
SCXCM_SLAVE	SCXBP_SCX_CLOCK_MODE parameter designates node as slave - i.e., to receive SCxbus clock from another SCxbus device
SCXCM_FALLBACK_MASTER	SCXBP_SCX_CLOCK_MODE parameter designates node to be SCxbus fallback master - i.e., to receive right SCxbus clock from another SCxbus device and to provide left SCxbus clock to be used by other SCxbus devices if the right SCxbus clock is unavailable
SCXST_SCX_RCLOCK	SCxbus right clock failed, use SCXBP_CLK_HISTORY parameter to retrieve
SCXST_SCX_LCLOCK	SCxbus left clock failed, use SCXBP_CLK_HISTORY parameter to retrieve
SCXST_SC_CLOCK	SCbus clock failed, use SCXBP_CLK_HISTORY parameter to retrieve
SCXST_SC_CLOCK_FAIL_SIG	SCbus clockfail signal detected, use SCXBP_CLK_HISTORY parameter to retrieve
SCXST_EXTCLOCK	SCxbus external clock failed, use SCXBP_CLK_HISTORY parameter to retrieve
SCXST_PLL_REF	PLL out-of-lock, use SCXBP_CLK_HISTORY parameter to retrieve
SCXST_CLK_RECOVER	Indicates failed clock recovered, use SCXBP_CLK_HISTORY parameter to retrieve

When the PLL process selects a clock source for a node, the following priorities apply in the order listed:

• For the node operating in the SCxbus Master state:
  • The clock source defined in the database (typically, the SCbus, the 8 kHz external reference clock from the SCxbus, or the local crystal oscillator)
  • The local crystal oscillator
• For the node operating in the SCxbus Fallback Master state:
  • SCxbus right clock
  • The clock source defined in the database
  • The local crystal oscillator
• For nodes operating as SCxbus slaves:
  • SCxbus right clock
  • SCxbus left clock
  • SCbus clock
  • Local crystal oscillator

4.5.3.  SCxbus Clock State Transitions

The SCxbus clock state transitions for each node are summarized in Figure 8.  SCxbus Clock States Transition Diagram. Table 9 defines the clock states in the diagram.

By starting with a current clock state, the diagram in Figure 8 illustrates the events and/or commands that can cause a transition from one state to another. To illustrate clock state transitions, the following description focuses on the clock transitions initiated by events or by application command for the following:

• Master state clock node
• Wait Master state clock node
• Fallback Master state clock node
• Wait Fallback Master state clock node

Figure 8.  SCxbus Clock States Transition Diagram

Table 9.  SCxbus Clock States

Clock State	Description
Master	The SCX160 SCxbus right clock is enabled, the left clock is disabled and the PLL clock is locked to the database or default value. If this master clock source fails or if the clocking configuration is changed by the scx_setbrdparm( ) function or if a SCbus clock event prevents the SCX160 SCxbus Adapter from being a viable SCxbus Master, then this node automatically switches to Wait Slave state.
Wait Master	The SCX160 SCxbus right and left clocks are disabled. If the SCxbus right clock is not present, this node automatically switches to Master state and provides SCxbus right clock to all other nodes.
Wait Slave	The SCX160 SCxbus right clock is enabled, the left clock is disabled and the PLL clock is locked to the database value or to the local crystal oscillator. In this state, the node is waiting for the SCxbus left clock to recover, at which point this node will automatically switch to Slave state.
Fallback Master	The SCX160 SCxbus right clock is disabled, the left clock is enabled and the PLL clock is locked to either the SCxbus right clock, the database value or the local crystal oscillator.
Wait Fallback Master	The SCX160 SCxbus right and left clocks are disabled. The PLL clock is locked to either the SCxbus right clock, the database value or the local crystal oscillator. If the SCxbus left clock is not present, this node automatically changes to Fallback Master state and starts providing SCxbus left clock.
Wait Fallback Slave	This SCX160 SCxbus right clock is disabled, the left clock is enabled and the PLL clock is locked to the database value or to the local crystal oscillatorIn this state, the node is waiting for the SCxbus right clock to recover, at which point this node will automatically switch to Slave state and disable the left SCxbus clock.
Slave	The SCX160 SCxbus right and left clocks are disabled. The PLL clock is locked to the highest priority good clock.

SCxbus Master State Clock Node Transitions

The node designated as the source of master clock to the SCxbus has its SCxbus right clock enabled and its left clock disabled. This node continues to provide SCxbus right clock until one of the following occurs:

• Its reference clock fails
• An SCbus state machine event occurs that indicates that this node can no longer provide reliable clock
• An application command is issued (using the scx_setbrdparm( ) function)

When any of the above events occur, this node transitions to the Wait Slave state as shown in Figure 8. The Wait Slave state is a transitory state during which the master clock node continues to provide SCxbus right clock until the node verifies the presence of the SCxbus left clock. If the SCxbus left clock is present, then this node transitions to the Slave state, as shown in Figure 8.

Alternatively, if during this period, the node's reference clock recovers or a SCbus state machine event indicates that this node is capable of providing master clock, then the node transitions to the Wait Master state, as shown in Figure 8.

In the Wait Master state, the node continually checks for the presence of the SCxbus right clock. When this clock is not detected, then this node automatically transitions to the Master state and provides master clocking on the SCxbus right clock line. This node will not take over as the master clock source as long as SCxbus right clock is being provided by another node.

SCxbus Wait Master State Clock Node Transitions

A node operating in the Slave state or the Wait Fallback Master state can be commanded by the scx_setbrdparm( ) function to transition to the Wait Master state, as shown in Figure 8.

In the Wait Master state, the node continually checks for the presence of the SCxbus right clock. When this clock is not detected, then this node automatically transitions to the Master state and provides master clocking on the SCxbus right clock line. This node will not take over as the master clock source as long as SCxbus right clock is being provided by another node.

SCxbus Fallback Master State Clock Node Transitions

The node designated as the source of fallback master clock to the SCxbus has its SCxbus right clock disabled and its left clock enabled. This node continues to provide SCxbus left clock until commanded to change to the Wait Fallback Slave state by the application.

The Wait Fallback Slave state is a transitory state during which the fallback master node continues to provide SCxbus left clock until the node verifies the presence of SCxbus right clock. If the SCxbus right clock is present, then this node transitions to the Slave state, as shown in Figure 8.

Alternatively, this node can be commanded to transition from the Wait Fallback Slave state to the Wait Fallback Master state. In this state, the node is slaved to the SCxbus clock; the SCxbus right and left clocks are disabled. In the Wait Fallback Master state, the node continually checks for the presence of the SCxbus left clock. When this clock is not detected, then this node automatically transitions to the Fallback Master state and provides fallback master clocking on the SCxbus left clock line. This node will not take over as the fallback master clock source as long as SCxbus left clock is being provided by another node.

SCxbus Wait Fallback Master State Clock Node Transitions

A node operating in the Slave state, the Wait Master state or the Wait Fallback Slave state can be commanded by the scx_setbrdparm( ) function to transition to the Wait Fallback Master state, as shown in Figure 8.

In the Wait Fallback Master state, the node continually checks for the presence of the SCxbus left clock. When this clock is not detected, then this node automatically transitions to the Fallback Master state and provides fallback master clocking on the SCxbus left clock line. This node will not take over as the fallback master clock source as long as SCxbus left clock is being provided by another node.

4.5.4.  SCbus Clock State Machine

The SCbus clock state machine controls the clocking on the SCbus interface of the SCX160 SCxbus Adapter. Its objective is to ensure that the SCbus always has a clock and to ensure that the SCX160 SCxbus Adapter never places a clock signal on a clocked SCbus. The SCbus clock state machine can automatically provide SCbus clock upon failure of the SCbus master clock.

The SCbus clock state machine changes from an existing state to a new state in response to a command from the application or an event such as a clock failure. See Table 10.  SCbus Clock State Transition Events for a summary of the commands and events that can cause a clock state transition in the SCbus state machine. To retrieve the values listed, use the scx_getbrdparm( ) function.

Table 10.  SCbus Clock State Transition Events

Parameter Value	Description
SCXCM_MASTER	SCXBP_SC_CLOCK_MODE parameter designates SCX160 to provide SCbus clock to the SCbus interface
SCXCM_SLAVE	SCXBP_SC_CLOCK_MODE parameter designates SCbus interface of SCX160 to receive SCbus clock, i.e., to become SCbus slave
SCXCM_FALLBACK_MASTER	SCXBP_SC_CLOCK_MODE parameter designates SCX160 to receive SCbus clock from another SCbus device and to provide fallback SCbus clock to be used by other SCbus devices if the master SCbus clock fails
SCXST_SC_CLOCK	SCbus clock faile, use SCXBP_CLK_HISTORY parameter to retrieve
SCXST_SC_CLOCK_FAIL_SIG	SCbus clockfail signal was asserted, use SCXBP_CLK_HISTORYparameter to retrieve
SCXST_CLK_RECOVER	Indicates failed clockrecovered, use SCXBP_CLK_HISTORY parameter to retrieve

4.5.5.  SCbus Clock State Transitions

The SCbus clock state transitions for each node are summarized in Figure 9.  SCbus Clock States Transition Diagram. Table 11 defines the clock states in the diagram.

Figure 9.  SCbus Clock States Transition Diagram

Table 11.  SCbus Clock States

Clock State	Description
Master	The SCX160 SCxbus Adapter's SCbus interface provides clock to the SCbus.
Fallback Master	The SCX160 SCxbus Adapter's SCbus clock driver is disabled (interface operates as a slave) until the master SCbus clock fails, at which point the SCX160 SCxbus Adapter automatically provides SCbus clock.
Wait Master	The SCX160 SCxbus Adapter's SCbus clock driver is disabled until the SCbus clock is no longer present, at which point the SCX160 SCxbus Adapter automatically provides SCbus clock.
Wait Slave	The SCX160 SCxbus Adapter's SCbus interface provides SCbus clock to the SCbus until another SCbus device uses the clockfail signal to indicate that it is ready to take over the task of providing SCbus clock.
Slave	The SCX160 SCxbus Adapter's SCbus interface is slaved to the SCbus clock. This state is changed by issuing a scx_setbrdparm( ) function that changes the SCXBP_SC_CLOCK_MODE parameter.

By starting with a current clock state, the diagram in Figure 9 illustrates the events and/or commands that can cause a transition from one state to another. To illustrate clock state transitions, the following description focuses on the clock transitions initiated by events or by application command for the following nodes:

• Master state clock node
• Wait Master state clock node
• Fallback Master state clock node

Since the SCxbus and the SCbus interfaces are relatively independently clocked, a node can operate with its SCbus interface in the Master State, the Fallback Master state or in the Slave state.

SCbus Master State Clock Node Transitions

In the SCbus Master state, the SCX160 SCxbus Adapter SCbus interface provides clock for all devices connected to the SCbus. The SCX160 SCxbus Adapter continues to provide SCbus clock until an SCxbus state machine event indicates that the SCX160 SCxbus Adapter can no longer provide reliable clock or by issuing an application command (using the scx_setbrdparm( ) function).

When either of the above events occurs, the SCbus interface transitions to the Wait Slave state (see Figure 9). The Wait Slave state is a transitory state during which the SCX160 SCxbus Adapter continues to provide clock to the SCbus until another SCbus device takes over this task. When the SCbus clockfail signal indicates that another SCbus device is ready to provide SCbus Clock, the SCbus interface transitions to the Slave state.

Alternatively, by application command, the SCbus interface can transition to the Wait Master state. In this state, the SCX160 SCxbus Adapter continually monitors the SCbus clockfail signal for loss of SCbus clock. When the SCbus clock is not present, the SCbus interface automatically transitions to the Master state and provides SCbus clock.

SCbus Wait Master State Clock Node Transitions

A SCbus interface operating in the Slave state, the Wait Slave State or the Fallback Master state can be commanded by the scx_setbrdparm( ) function to transition to the Wait Master state, as shown in Figure 9.

In the Wait Master state, the SCbus interface continually monitors the SCbus clockfail signal for the absence of SCbus clock. When this clock is not present, then the SCbus interface automatically transitions to the Master state and provides SCbus clocking. The SCbus interface will not take over as the master clock source as long as SCbus clock is being provided by another device connected to the SCbus.

SCbus Fallback Master State Clock Node Transitions

The SCX160 SCxbus Adapter SCbus interface can be designated as fallback master source for SCbus clock. When the SCbus interface is operating in the Fallback Master state, the SCX160 SCxbus Adapter continually monitors the SCbus clockfail signal for the presence of SCbus clock. When SCbus clock is not present, then the SCbus interface automatically transitions to the Wait Master state, as shown in Figure 9.

In the Wait Master state, the SCX160 SCxbus Adapter checks for the absence of clock on the SCbus. If no clock signal is detected, then the SCbus interface transitions to the Master state.

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