MN102L00 SERIES INSTRUCTION SET

Table of Contents
    Transfer instruction
        mov     movx    movb    movbu
        ext     extx    extxu   extxb   extxbu
    Calculation instruction
        add     addc    addnf   sub     subc
        mul     mulu    divu
    Compare, logical operators
        cmp     and     or      xor     not
    Rotate, shift
        asr     lsr     ror     rol
    Bit operation
        btst    bset    bclr
    Division
        beq     bne     blt     ble     bge     bgt
        bcs     bls     bcc     bhi     bvc     bvs
        bnc     bns     bra
        beqx    bnex    bltx    blex    bgex    bgtx
        bcsx    blsx    bccx    bhix    bvcx    bvsx
        bncx    bnsx
    Jump, call
        jmp     jsr     nop     rts     rti
    INSTRUCTION SET Structure




    Transfer instruction
                                                        Flag
                                                OP  V C N Z V C N Z Cod Cy-
Mnemonic            Operation                   EX. X X X X F F F F Siz cle
mov Dm,An           ;Dm->An                     -   - - - - - - - - 2   2
mov An,Dm           ;An->Dm                     -   - - - - - - - - 2   2
mov Dn,Dm           ;Dn->Dm                     -   - - - - - - - - 1   1
mov An,Am           ;An->Am                     -   - - - - - - - - 2   2
mov psw,Dn          ;psw->Dn                    0   - - - - - - - - 2   2
mov Dn,psw          ;Dn->psw                    -   # # # # # # # # 2   2
mov MDR,Dn          ;MDR->Dn                    0   - - - - - - - - 2   2
mov Dn,MDR          ;Dn->MDR                    -   - - - - - - - - 2   2

mov (An),Dm         ;mem16(An)->Dm              S   - - - - - - - - 1   1
mov (d8,An),Dm      ;mem16(An+d8)->Dm           S   - - - - - - - - 2   1
mov (d16,An),Dm     ;mem16(An+d16)->Dm          S   - - - - - - - - 4   2
mov (d24,An),Dm     ;mem16(An+d24)->Dm          S   - - - - - - - - 5   3
mov (Di,An),Dm      ;mem16(An+Di)->Dm           S   - - - - - - - - 2   2
mov (abs16),Dn      ;mem16(abs16)->Dn           S   - - - - - - - - 3   2
mov (abs24),Dn      ;mem16(abs24)->Dn           S   - - - - - - - - 5   3

mov (An),Am         ;mem24(An)->Am              -   - - - - - - - - 2   2
mov (d8,An),Am      ;mem24(An+d8)->Am           -   - - - - - - - - 2   2
mov (d16,An),Am     ;mem24(An+d16)->Am          -   - - - - - - - - 4   3
mov (d24,An),Am     ;mem24(An+d24)->Am          -   - - - - - - - - 5   4
mov (Di,An),Am      ;mem24(An+Di)->Am           -   - - - - - - - - 2   3
mov (abs16),An      ;mem24(abs16)->An           -   - - - - - - - - 4   3
mov (abs24),An      ;mem24(abs24)->An           -   - - - - - - - - 5   4

mov Dm,(An)         ;Dm->mem16(An)              -   - - - - - - - - 1   1
mov Dm,(d8,An)      ;Dm->mem16(An+d8)           -   - - - - - - - - 2   1
mov Dm,(d16,An)     ;Dm->mem16(An+d16)          -   - - - - - - - - 4   2
mov Dm,(d24,An)     ;Dm->mem16(An+d24)          -   - - - - - - - - 5   3
mov Dm,(Di,An)      ;Dm->mem16(An+Di)           -   - - - - - - - - 2   2
mov Dn,(abs16)      ;Dn->mem16(abs16)           -   - - - - - - - - 3   1
mov Dn,(abs24)      ;Dn->mem16(abs24)           -   - - - - - - - - 5   3

mov Am,(An)         ;Am->mem24(An)              -   - - - - - - - - 2   2
mov Am,(d8,An)      ;Am->mem24(An+d8)           -   - - - - - - - - 2   2
mov Am,(d16,An)     ;Am->mem24(An+d16)          -   - - - - - - - - 4   3
mov Am,(d24,An)     ;Am->mem24(An+d24)          -   - - - - - - - - 5   4
mov Am,(Di,An)      ;Am->mem24(An+Di)           -   - - - - - - - - 2   3
mov An,(abs16)      ;An->mem24(abs16)           -   - - - - - - - - 4   3
mov An,(abs24)      ;An->mem24(abs24)           -   - - - - - - - - 5   4

mov imm8,Dn         imm8->Dn                    S   - - - - - - - - 2   1
mov imm16,Dn        imm16->Dn                   S   - - - - - - - - 3   1
mov imm24,Dn        imm24->Dn                   -   - - - - - - - - 5   3
mov imm16,An        imm16->An                   0   - - - - - - - - 3   1
mov imm24,An        imm24->An                   -   - - - - - - - - 5   3

movx (d8,An),Dm     ;mem24(An+d8)->Dm           -   - - - - - - - - 3   3
movx (d16,An),Dm    ;mem24(An+d16)->Dm          -   - - - - - - - - 4   3
movx (d24,An),Dm    ;mem24(An+d24)->Dm          -   - - - - - - - - 5   4
movx Dm,(d8,An)     ;Dm->mem24(An+d8)           -   - - - - - - - - 3   3
movx Dm,(d16,An)    ;Dm->mem24(An+d16)          -   - - - - - - - - 4   3
movx Dm,(d24,An)    ;Dm->mem24(An+d24)          -   - - - - - - - - 5   4

movb (An),Dm        ;mem8(An)->Dm               S   - - - - - - - - 2   2
movb (d8,An),Dm     ;mem8(An+d8)->Dm            S   - - - - - - - - 3   2
movb (d16,An),Dm    ;mem8(An+d16)->Dm           S   - - - - - - - - 4   2
movb (d24,An),Dm    ;mem8(An+d24)->Dm           S   - - - - - - - - 5   3
movb (Di,An),Dm     ;mem8(An+Di)->Dm            S   - - - - - - - - 2   2
movb (abs16),Dn     ;mem8(abs16)->Dn            S   - - - - - - - - 4   2
movb (abs24),Dn     ;mem8(abs24)->Dn            S   - - - - - - - - 5   3

movb Dm,(An)        ;Dm->mem8(An)               -   - - - - - - - - 1   1
movb Dm,(d8,An)     ;Dm->mem8(An+d8)            -   - - - - - - - - 3   2
movb Dm,(d16,An)    ;Dm->mem8(An+d16)           -   - - - - - - - - 4   2
movb Dm,(d24,An)    ;Dm->mem8(An+d24)           -   - - - - - - - - 5   3
movb Dm,(Di,An)     ;Dm->mem8(An+Di)            -   - - - - - - - - 2   2
movb Dn,(abs16)     ;Dn->mem8(abs16)            -   - - - - - - - - 3   1
movb Dn,(abs24)     ;Dn->mem8(abs24)            -   - - - - - - - - 5   3

movbu (An),Dm       ;mem8(An)->Dm               0   - - - - - - - - 1   1
movbu (d8,An),Dm    ;mem8(An+d8)->Dm            0   - - - - - - - - 3   2
movbu (d16,An),Dm   ;mem8(An+d16)->Dm           0   - - - - - - - - 4   2
movbu (d24,An),Dm   ;mem8(An+d24)->Dm           0   - - - - - - - - 5   3
movbu (Di,An),Dm    ;mem8(An+Di)->Dm            0   - - - - - - - - 2   2
movbu (abs16),Dn    ;mem8(abs16)->Dn            0   - - - - - - - - 3   1
movbu (abs24),Dn    ;mem8(abs24)->Dn            0   - - - - - - - - 5   3

ext Dn              ;if Dn.bp15=0 then          S   - - - - - - - - 2   3
                    ; x'0000'->MDR
                    ;else
                    ; x'ffff'->MDR

extx Dn             ;if Dn.bp15=0 then          S   - - - - - - - - 1   1
                    ; Dn&x'00ffff'->Dn
                    ;else
                    ; Dn|x'ff0000'->Dn

extxu Dn            ;Dn&x'00ffff'->Dn           0   - - - - - - - - 1   1

extxb Dn            ;if Dn.bp7=0 then           S   - - - - - - - - 1   1
                    ; Dn&x'0000ff'->Dn
                    ;else
                    ; Dn|x'ffff00'->Dn

extxbu Dn           ;Dn&x'0000ff'->Dn           0   - - - - - - - - 1   1

    Calculation instruction
add Dn,Dm           ;Dm+Dn->Dm                  -   # # # # # # # # 1   1
add Dm,An           ;An+Dm->An                  -   # # # # # # # # 2   2
add An,Dm           ;Dm+An->Dm                  -   # # # # # # # # 2   2
add An,Am           ;Am+An->Am                  -   # # # # # # # # 2   2

add imm8,Dn         ;Dn+imm8->Dn                S   # # # # # # # # 2   1
add imm16,Dn        ;Dn+imm16->Dn               S   # # # # # # # # 4   2
add imm24,Dn        ;Dn+imm24->Dn               -   # # # # # # # # 5   3
add imm8,An         ;An+imm8->An                S   # # # # # # # # 2   1
add imm16,An        ;An+imm16->An               S   # # # # # # # # 4   2
add imm24,An        ;An+imm24->An               -   # # # # # # # # 5   3

addc Dn,Dm          ;Dm+Dn+CF->Dm               -   # # # # # # # # 2   2
addnf imm8,An       ;An+imm8->An                S   - - - - - - - - 3   2

sub Dn,Dm           ;Dm-Dn->Dm                  -   # # # # # # # # 1   1
sub Dm,An           ;An-Dm->An                  -   # # # # # # # # 2   2
sub An,Dm           ;Dm-An->Dm                  -   # # # # # # # # 2   2
sub An,Am           ;Am-An->Am                  -   # # # # # # # # 2   2

sub imm16,Dn        ;Dn-imm16->Dn               S   # # # # # # # # 4   2
sub imm24,Dn        ;Dn-imm24->Dn               -   # # # # # # # # 5   3
sub imm16,An        ;An-imm16->An               S   # # # # # # # # 4   2
sub imm24,An        ;An-imm24->An               -   # # # # # # # # 5   3

subc Dn,Dm          ;Dm-Dn-CF->Dm               -   # # # # # # # # 2   2

mul Dn,Dm           ;Dm*Dn->Dm,(Dm*Dn)>>16->MDR -   ? ? ? ? 0 ? # # 2   12
mulu Dn,Dm          ;Dm*Dn->Dm,(Dm*Dn)>>16->MDR -   ? ? ? ? 0 ? # # 2   12
divu Dn,Dm          ;(MDR<<16+Dm)/Dn->Dm,...MDR -   ? ? #?#?01? #?#?2   13

    Compare, logical operators
cmp Dn,Dm           ;Dm-Dn                      -   # # # # # # # # 2   2
cmp Dm,An           ;An-Dm                      -   # # # # # # # # 2   2
cmp An,Dm           ;Dm-An                      -   # # # # # # # # 2   2
cmp An,Am           ;Am-An                      -   # # # # # # # # 2   2

cmp imm8,Dn         ;Dn-imm8                    S   # # # # # # # # 2   1
cmp imm16,Dn        ;Dn-imm16                   S   # # # # # # # # 4   2
cmp imm24,Dn        ;Dn-imm24                   -   # # # # # # # # 5   3
cmp imm16,An        ;An-imm16                   0   # # # # # # # # 3   1
cmp imm24,An        ;An-imm24                   -   # # # # # # # # 5   3

and Dn,Dm           ;Dm&(x'ff0000'|Dn)->Dm      -   - - - - 0 0 # # 2   2
and imm8,Dn         ;Dn&(x'ff0000'+imm8)->Dn    0   - - - - 0 0 # # 3   2
and imm16,Dn        ;Dn&(x'ff0000'+imm16)->Dn   -   - - - - 0 0 # # 4   2
and imm16,psw       ;psw&imm16->psw             -   # # # # # # # # 4   3

or Dn,Dm            ;Dm|(Dn&x'00ffff')->Dm      -   - - - - 0 0 # # 2   2
or imm8,Dn          ;Dn|imm8->Dn                0   - - - - 0 0 # # 3   2
or imm16,Dn         ;Dn|imm16->Dn               -   - - - - 0 0 # # 4   2
or imm16,psw        ;psw|imm16->psw             -   # # # # # # # # 4   3

xor Dn,Dm           ;Dm^(x'00ffff'&Dn)->Dm      -   - - - - 0 0 # # 2   2
xor imm16,Dn        ;Dn^imm16->Dn               -   - - - - 0 0 # # 4   2

not Dn              ;Dn^x'00ffff'->Dn           -   - - - - 0 0 # # 2   2

    Rotate, shift
asr Dn              ;bp15->bp15..bp0->CF        -   - - - - 0 # # # 2   2
lsr Dn              ;   0->bp15..bp0->CF        -   - - - - 0 # # # 2   2
ror Dn              ;  CF->bp15..bp0->CF        -   - - - - 0 # # # 2   2
rol Dn              ;  CF<-bp15..bp0<-CF        -   - - - - 0 # # # 2   2

    Bit operation
btst imm8,Dn        ;Dn&imm8...psw              0   - - - - 0 0 0 # 3   2
btst imm16,Dn       ;Dn&imm16...psw             0   - - - - 0 0 # # 4   2
bset Dm,(An)        ;mem8(An)&Dm...psw          0   - - - - 0 0 0 # 2   5
                    ;mem8(An)|Dm->mem8(An)
bclr Dm,(An)        ;mem8(An)&Dm...psw          0   - - - - 0 0 0 # 2   5
                    ;mem8(An)&Dm->mem8(An)

    Division
beq label           ;if ZF=1 then jp d8(label)  -   - - - - - - - - 2   2/1
bne label           ;if ZF=0 then jp d8(label)  -   - - - - - - - - 2   2/1
blt label           ;if (VF^NF)=1 then jp       -   - - - - - - - - 2   2/1
ble label           ;if ((VF^NF)|ZF)=1 then jp  -   - - - - - - - - 2   2/1
bge label           ;if (VF^NF)=0 then jp       -   - - - - - - - - 2   2/1
bgt label           ;if ((VF^NF)|ZF)=0 then jp  -   - - - - - - - - 2   2/1
bcs label           ;if CF=1 then jp d8(label)  -   - - - - - - - - 2   2/1
bls label           ;if (CF|ZF)=1 then jp       -   - - - - - - - - 2   2/1
bcc label           ;if CF=0 then jp d8(label)  -   - - - - - - - - 2   2/1
bhi label           ;if (CF|ZF)=0 then jp       -   - - - - - - - - 2   2/1
bvc label           ;if VF=0 then jp d8(label)  -   - - - - - - - - 3   3/2
bvs label           ;if VF=1 then jp d8(label)  -   - - - - - - - - 3   3/2
bnc label           ;if NF=0 then jp d8(label)  -   - - - - - - - - 3   3/2
bns label           ;if NF=1 then jp d8(label)  -   - - - - - - - - 3   3/2
bra label           ;jp d8(label)               -   - - - - - - - - 2   2

beqx label          ;if ZX=1 then jp d8(label)  -   - - - - - - - - 3   3/2
bnex label          ;if ZX=0 then jp d8(label)  -   - - - - - - - - 3   3/2
bltx label          ;if (VX^NX)=1 then jp       -   - - - - - - - - 3   3/2
blex label          ;if ((VX^NX)|ZX)=1 then jp  -   - - - - - - - - 3   3/2
bgex label          ;if (VX^NX)=0 then jp       -   - - - - - - - - 3   3/2
bgtx label          ;if ((VX^NX)|ZX)=0 then jp  -   - - - - - - - - 3   3/2
bcsx label          ;if CX=1 then jp d8(label)  -   - - - - - - - - 3   3/2
blsx label          ;if (CX|ZX)=1 then jp       -   - - - - - - - - 3   3/2
bccx label          ;if CX=0 then jp d8(label)  -   - - - - - - - - 3   3/2
bhix label          ;if (CX|ZX)=0 then jp       -   - - - - - - - - 3   3/2
bvcx label          ;if VX=0 then jp d8(label)  -   - - - - - - - - 3   3/2
bvsx label          ;if VX=1 then jp d8(label)  -   - - - - - - - - 3   3/2
bncx label          ;if NX=0 then jp d8(label)  -   - - - - - - - - 3   3/2
bnsx label          ;if NX=1 then jp d8(label)  -   - - - - - - - - 3   3/2

    Jump, call
jmp label16         ;PC+3+d16(label16)->PC      -   - - - - - - - - 3   2
jmp label24         ;PC+5+d24(label24)->PC      -   - - - - - - - - 5   4
jmp (An)            ;An->PC                     -   - - - - - - - - 2   3

jsr label16         ;A3-4->A3                   -   - - - - - - - - 3   4
                    ;PC+3->mem24(A3)
                    ;PC+3+d16(label16)->PC
jsr label24         ;A3-4->A3                   -   - - - - - - - - 5   5
                    ;PC+5->mem24(A3)
                    ;PC+5+d24(label24)->PC
jsr (An)            ;A3-4->A3                   -   - - - - - - - - 2   5
                    ;PC+2->mem24(A3)
                    ;An->PC

nop                 ;PC+1->PC                   -   - - - - - - - - 1   1

rts                 ;mem24(A3)->PC              -   - - - - - - - - 1   5
                    ;A3+4->A3
rti                 ;mem16(A3)->psw             -   # # # # # # # # 1   6
                    ;mem24(A3+2)->PC

    INSTRUCTION SET structure
Meaning of Abbreviation used in Table
    Dn,Dm,Di                Data register (D0,D1,D2,D3)
    An,Am                   Address register (A0,A1,A2,A3)
    MDR,psw                 Multiplication/Division register, program status word
    PC                      Program counter
    imm8,imm16,imm24        Constant
    d8,d16,d24              Displacement
    abs8,abs16,abs24        Absolute address
    mem8(),mem16(),mem24()  8,16,24 bit data that is referred by the address in ()
    bp15,bp15..0,bp0        Register bit specification
    &,|,^                   AND, OR, XOR (exclusive-OR)
    ~,<<,>>                 Bit rotation, bit shift
    VX,CX                   Extension overflow flag, extension carry flag
    NX,ZX                   Extension negative flag, extension zero flag
    VF,CF                   Overflow flag, carry flag
    NF,ZF                   Negative flag, zero flag
    ->,...                  Assign, reflection of calculation result
OP EX.(operand extension)        Flag
    0       Zero extension          #       Changed
    S       Signal extension        -      Not changed
    -       No relation             0       Always 0
                                    1       Always 1
                                    ?       not consistent
Cod Siz                       Cycle
    Code size                       The shortest cycle number should be written.
    Unit byte                       Unit: machine cycle
                                    a/b: there is a division in a, but no division in b.
Cautions
    The instruction that accesses to 16 bit and 24 bit data should have even number memory address.
    All 8 bit (d8) and 16 bit (d16) displacements should be signal extension.

===============================================================================
 Copyright (c) 1998-1999.  Seiko Instruments Inc.  All rights reserved. 
===============================================================================
