1. A script is provided in syn/ to synthesize the model to gate level. In the dc_shell run leon.dcsh (i.e. run "dc_shell -f leon.dcsh")
2. A file called leon_gate.vhd will be produced. You will need to modify some of this code since we do not have the necessary libraries. For each instance of a syncram component you will need to map it back to a generic componet. A sample of the modified lines are outlined in red. Notice in the modified code when you use the generic map you need to match the number you are mapping to the number listed in the entity name. For example, if you have a syncram_abits7_dbits25_0 then you will have a generic map(7,25). If you have a syncram_abits9_dbits32_0 then you will have a generic map(9,32).
   
   

   SAMPLE OUTPUT AFTER SYNTHESIS

   entity syncram_abits7_dbits25_0 is     port( address : in std_logic_vector (0 to 6); clk : in std_logic;            datain : in std_logic_vector (0 to 24); dataout : out            std_logic_vector (0 to 24); enable, write : in std_logic); end syncram_abits7_dbits25_0; architecture SYN of syncram_abits7_dbits25_0 is     component generic_syncram_param_1_2           port( address : in std_logic_vector (0 to 6); clk : in std_logic;                 datain : in std_logic_vector (0 to 24); dataout : out                 std_logic_vector (0 to 24); enable, write : in std_logic);     end component; begin u0 : generic_syncram_param_1_2 port map( address(0) => address(0), ....

   SAMPLE MODIFIED OUTPUT

   entity syncram_abits7_dbits25_0 is     port( address : in std_logic_vector (0 to 6); clk : in std_logic;           datain : in std_logic_vector (0 to 24); dataout : out           std_logic_vector (0 to 24); enable, write : in std_logic); end syncram_abits7_dbits25_0; architecture SYN of syncram_abits7_dbits25_0 is     component generic_syncram        generic ( abits : integer := 10; dbits : integer := 8 );        port( address : in std_logic_vector (0 to 6); clk : in std_logic;               datain : in std_logic_vector (0 to 24); dataout : out               std_logic_vector (0 to 24); enable, write : in std_logic);     end component; begin u0 : generic_syncram generic map(7,25) port map( address(0) => address(0), ...

   
   
3. The modified leon_gate.vhd needs to be moved to ../source/leon/leon_gate.vhd.
4. Next we analyze the files using the Makefile provided in source/ by running "make syn"
5. Run "vhdldbx" to simulate, your top level entity is TBDEF

1. you will first need a run script to indicate how long the test bench will run for. This number is dependent upon the application you are running. A default one is provided in run.scr
2. you need to analyze the necessary files, since we are looking at the gate level we can used the Makefile provided in source/ by running "make syn".
3. now we simulate it to produce a toggle file "vhdlsim -i run.scr -togfile leon_tc -power_stats TBDEF". From this command we will produce a toggle file called leon_tc
4. We now convert the toggle file format using sim2dp with the following command, "sim2dp -vss leon_tc > leon_sa.scr" The new file is called leon_sa.scr
5. Now that we have a readable toggle file we will now use dc_shell to analyze it. A script is provided in scripts/ so we run "dc_shell -f power.scr". After this step completes you will have the power consumption of LEON.

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