----------------------- Release 1.2.0-b4121 ---------------------------- 2012-12-20 Added ISE14.3 and PlanAhead support for Virtex 6 and Spartan 6 template designs. 2012-12-19 DDRSPA: Add phy implementation config VHDL generic (phyiconf) 2012-12-17 GRETH: Support larger frames (maxsize VHDL generic added) 2012-12-16 Added (experimental) support for Zynq-7000 and ZedBoard (leon3-digilent-xc7z020). 2012-12-16 Added support for Xilinx VC707 and KC705 development kits (leon3-xilinx-vc707 and leon3-xilinx-kc705) 2012-12-16 Added support for Xilinx Vivado flow 2012-12-16 Added support for Xilinx 7-series FPGAs (Virtex, Kintex, Artix) 2012-12-16 LEON: Fix possible pipeline hang after two consecutive DIV operations. Bad sequence is not generated by compilers. 2012-12-14 leon3-gr-xc6s: Remove USBDC* from template design 2012-12-10 PCIPADS: Allow to select voltage and level via VHDL generics 2012-12-10 GRGPIO: Add capability register and increase core revision to 2 2012-12-07 DDRSPA: Fix reset delay bug in controller when pwron=0 2012-11-28 SPICTRL: Use testoen to control direction in test mode 2012-11-28 GRETH: Use testoen to control direction of mdio in test mode 2012-11-19 GRGPIO: Use testoen to control direction in test mode. 2012-11-17 Added AMBA test framework documentation to configuration guide 2012-11-17 Added option to select predefined example processor configurations in xconfig. 2012-11-15 JTAG: Add oepol generic to control polarity of tdoen signal Connect tdoen signal in the leon3-asic example design 2012-11-13 Added PWM Generator (GRPWM) to COM and FT distributions 2012-11-13 Added memory scrubber (MEMSCRUB) to FT distributions 2012-11-06 Remove HCACHE signal from AMBA records. This change may break existing external IP cores. 2012-10-29 Added NAND Flash Memory Controller (NANDFCTRL) IP core (to COM and FT releases). 2012-10-24 Makefile: added DESIGNER_LAYOUT_OPT to override all Designer layout options. 2012-10-22 Added disable during scan test handling to syncram techmap. Distribute testin vector for syncrams in AMBA records. Updated GRLIB documentation on scan test support. 2012-10-15 Added LEON/GRLIB design and configuration guide (doc/guide.pdf) 2012-10-13 Remove ATACTRL 2012-10-12 LEON/SRMMU: Allow 64 TLB entries (for each TLB) 2012-10-12 Update GRLIB config package with grlib_config_array constant. All local copies of the global configuration package needs to be updated. All cores that make use of grlib_debug_* constants need to be changed to use grlib_config_array(grlib_debug_*). 2012-10-11 LEON: Update IP core doc. regarding types of bus accesses performed by the processors. 2012-10-03 DDRSPA,DDR2SPA: Add hooks for scan test support 2012-09-30 Update Aldec riviera targets to work with current versions. 2012-09-27 LEON3: Part of partially filled I-cache line could get incorrectly marked as valid when executing branch instruction with I-cache frozen and branch prediction enabled. Does not affect LEON3FT. 2012-09-26 AHBRAM: Fix bug in wait state generation when pipe=1 2012-09-25 GRETH: Add generic to extend MDIO output hold time to more than one AMBA cycle. 2012-09-25 GRCLKGATE: Add optional extra input for ungating all clocks 2012-09-25 GRCLKGATE: Propagate master reset asynchronously into gated resets by logical AND:ing. 2012-09-24 Added IOMMU (GRIOMMU) to LEON4 relases. 2012-09-23 Removed CoreMP7 to GRLIB bridge and design. 2012-09-23 Removed WildCard design and WILD2AHB core. 2012-09-23 Removed HAPS files. 2012-09-11 AHBCTRL/AHBCTRL_MB: Treat HLOCK as coupled to specific access to prevent HMASTLOCK assertion for normal accesses that receive a SPLIT/RETRY response. 2012-09-06 Use VERILOGSYNFILES in script generation for XST and Synplify. 2012-09-06 Remove basic_passthru design 2012-09-06 Remove unmaintained designs leon3-ge-hpe-mini, -lattice and leon3-ge-hpe-midi-ep2s180. Also removed libraries and cores that were only used in these designs. Vendor and device IDs are kept and files can manually be copied from older GRLIB releases. 2012-08-24 SPICTRL: Core would generate one extra SCK cycle after last word in queue for FACT = 1 and CPHA = 1. 2012-08-24 SPICTRL: Fix transmit queue race condition introduced in 1.1.0-b4108 that could result in corrupted transmit data. 2012-07-20 GRGPIO: irqgen=2,3,4 led to all irqmap registers getting the same value on writes. 2012-07-11 I-cache flush via ASI 0x10 was a no-op for systems implemented without MMU. 2012-06-261 DDRSPA,DDR2SPA: Move reset delay from phy to controller. 2012-06-151 DDRSPA,DDR2SPA: Remove the internal fast generic, use read counters to get correct behavior for all speed ratios with the same controller. 2012-05-10 DDRSPA,DDR2SPA: Moved ddr2spa and ddrspa components into their own package ddrpkg. Make older versions of ddr controllers available again under ddrv1 directory. DDRSPA: Re-implemented to use the same structure as DDR2SPA. DDRSPA: Add support for control signal timing up to DDR400. 2012-04-30 SPIMCTRL: Allow user to specify address offset for SPI device. 2012-04-25 leon3-gr-xc6: RGMII interface did not work with 10/100 MAC. 2012-04-24 leon3-xilinx-sp601: USB/UART had swapped RX/TX signals. 2012-04-12 Merged Xilinx ML505 - ML509 template designs into the design leon3-xilinx-ml50x and added option to use the DDR2 MIG. 2012-04-11 Added template design for TerASIC DE0-Nano board (leon3-terasic-de0-nano) 2012-03-19 Automatically perform "vsim-fix" when generating ModelSim scripts to avoid issues with ':' in paths in Cygwin. 2012-03-05 GRACECTRL: Emulate 16-bit mode for 8-bit MPU interface. Enable core for Xilinx ML605 and SP605 template designs. 2012-02-28 LEON3/4: Corrected documentation on cache flush ASIs. ----------------------- Release 1.1.0-b4113 ---------------------------- 2012-01-18 Added template design for ZTEX USB-FPGA Module 1.15 (leon3-ztex-ufm-115). Renamed leon3-ztex-ufm-xc6slx25 to leon3-ztex-ufm-111. 2012-01-10 Moved I2C and SPI cores to separate directories. ----------------------- Release 1.1.0-b4112 ---------------------------- 2012-01-02 Added template design for Xilinx SP605 board 2011-12-29 Added template design for ZTEX USB-FPGA Module 1.11 (leon3-ztex-ufm-xc6slx25) 2011-12-28 Added SPI to AHB bridge (SPI2AHB) core ----------------------- Release 1.1.0-b4111 ---------------------------- 2011-12-19 Added RGMII interface for GR-XC6S-LX75 board. 2011-11-29 Work-around for Xilinx SecureIP compilation bug 2011-11-29 Added MIG wrapper to a few additional template designs 2011-11-28 Added support for Xilinx ISIM simulator. 2011-11-18 Improved Actel Libero script generation 2011-10-14 MMU system test software: Do not use %local register in leaf function. Could lead to test freeze with GCC 4.4.2. 2011-10-06 DDR2SPA: Added support for registered SDRAM, and read-only tech field to DDR2CFG2 register. Increased core revision to 1 in PnP entry. 2011-09-29 SPICTRL: User was allowed to start a new transfer before SCK had transitioned to idle state. If a transfer was started early this could affect the clock phase for CPHA = 0. 2011-09-26 Removed script support for early versions of eTools 2011-09-26 Updated SPICTRL to rev 5 adding SCK filtering in slave mode 2011-09-18 Added "Extending the xconfig GUI configuration" section to GRLIB User's Manual (grlib.pdf). 2011-09-18 Added I2C to AHB bridge (I2C2AHB) core 2011-09-06 AHBCTRL: Update memory map intersection checks and clarify in documentation that the AHB I/O area can be placed within a slave memory area 2011-08-06 Enable 16-bit FLASH interface in leon3-nuhorizon design 2011-07-06 I2CMST: Added option to use dynamic filter ----------------------- Release 1.1.0-b4108 ---------------------------- 2011-06-15 Added DDR2 MIG wrapper for template design for Xilinx SP601 Spartan6 board. 2011-06-13 Added template design for new Pender Spartan-6 board, including a wrapper for Xilinx MIG 16-bit DDR2 controller. 2011-06-13 Added template designs for Xilinx ML605 board, including a wrapper for Xilinx MIG 64-bit DDR3 controller. 2011-06-01 Added template design for Altera DE2 board, including 16-bit SDRAM controller. 2011-05-18 SPICTRL: Allow use of SYNCRAM_2P for buffers 2011-04-12 Expanded section "9. Extending GRLIB" of GRLIB User's Manual 2011-03-17 Added AHBTRACE_MMB capable of multi-bus tracing. 2011-01-31 GRFPU-lite netlists for Altera could not be synthesized 2011-01-13 SPICTRL: 3-wire transfer direction order can now be configured 2011-01-09 Added template design for BeMicro SDK (leon3-arrow-bemicro-sdk) 2011-01-04 Hynix DDR2 model, fix spurious error messages in simulation ----------------------- Release 1.1.0-b4105 ---------------------------- 2010-11-29 DDR2SPA: Fast acknowlege on read was one cycle too early 2010-11-22 DDR2SPA: Fix data selection for AHB buses wider than 2xDDR 2010-11-17 DDR2SPA: Write mode register correctly based on CAS/TWR settings 2010-11-15 DDR2SPA: Add bigmem generic to enable >1GB RAM bank support 2010-11-16 APBUART: Set number of scaler bits via VHDL generic 2010-11-15 DDR2SPA: Separate reset generation for AHB/DDR clock domains 2010-11-12 GPTIMER: Allow external watchdog enable/disable. ----------------------- Release 1.1.0-b4104 ---------------------------- 2010-10-29 Added design for TerASIC Altera Cyclone-IV DE2-115 board 2010-10-29 Improved flow for Quartus-10 2010-10-14 DDR2SPA: Reimplement DDR2 controller to merge all data sizes. ----------------------- Release 1.1.0-b4102 ---------------------------- 2010-10-12 Support for Xilinx ISE12 flow. 2010-10-01 Improved generation of Actel Libero project file to avoid large amount of bogus warnings. 2010-09-23 DDR2SPA: Support single-ended DQS for Virtex4-6 2010-09-12 GPTIMER: IP field in timer control register is now write-clear 2010-08-09 GRGPIO: Add generic to specify the first interrupt line the core should drive. Add support to dynamically specify the interrupt line to use for each GPIO line. 2010-06-28 Added Testbench framework for PCI. 2010-06-28 PCI_TARGET: Added support for PCI bus in big-little mode and support for byte and half word PCI accesses. 2010-06-07 I2CMST/I2CSLV: Added generic that adjusts low-pass filter 2010-05-19 AHBJTAG: Use bit 32 in read data to indicate if AHB access has finished. Increased core version to 1. 2010-05-10 SPICTRL: Extended system test with test that uses an external simulation device. Function now has one additional argument. 2010-05-06 XST: Remove -read_cores yes from XST script generation as yes is the default read_cores setting. This allows specifying -read_cores yes, no or optimize via the XSTOPT variable. 2010-05-05 FPU: GRFPU and GRFPU-lite netlists in both LEON3 and LEON4 versions are now available for Cyclone2, Cyclone3, Stratix2, Stratix3, Spartan3, Virtex2, Virtex4 and Virtex5. 2010-05-05 FPU: Always use FPU netlists in distributions lacking FPU source code. 2010-05-05 FPU: Use EDIF netlists for FPU netlist synthesis on Xilinx 2010-03-21 Improved input data filtering in serial DSU link (DCOM_UART). 2010-02-15 Added template design for Xilinx SP601 Spartan6 board 2010-02-01 Support for 64- and 128-bit AHB buses