; Copyright (c) 2009, RISC OS Open Ltd
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;     * Redistributions of source code must retain the above copyright
;       notice, this list of conditions and the following disclaimer.
;     * Redistributions in binary form must reproduce the above copyright
;       notice, this list of conditions and the following disclaimer in the
;       documentation and/or other materials provided with the distribution.
;     * Neither the name of RISC OS Open Ltd nor the names of its contributors
;       may be used to endorse or promote products derived from this software
;       without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY RISC OS OPEN LTD ''AS IS'' AND ANY EXPRESS OR
; IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
; MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
; EVENT SHALL RISC OS OPEN LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
; ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.


; Historically, RISC OS has usually tried to cater for all CPU types at run
; time. This was partly because CPUs were swappable in some machines, and
; partly because of economies of scale when manufacturing masked ROMs. Neither
; of these arguments are as important in today's environment.
;
; It is probably desirable for disc components to continue to be as widely
; applicable as possible to help with version control. However, there may be
; exceptions in certain cases, e.g. codecs will often want to be tuned to a
; specific architecture. But ROM builds can benefit, in terms of code size,
; speed and maintainability, from being targetted at the correct CPU -
; previously, such customisation was mainly confined to the FPASC/FPEmulator.
;
; This header file translates between the "Machine" build variable and a set of
; assembly-time variables that describe the range of CPUs which must be
; supported by that build. Thus, the author of the software can switch
; depending upon the specific CPU feature that they require, and build
; maintainers can select the range of CPUs that a given build must run on.
; Typically, except for IOMD machines, a ROM build will only target one CPU,
; but a disc build will target a wide range of CPUs.
;
; The assembler variables are of the form
;
;  SupportARMvx -> at least one supported platform is of architecture x or later
;  NoARMvx      -> at least one supported platform is of architecture before x
;
; or for architecture variants (usually a single letter), the variables
; indicate whether one or more supported platforms do or don't support that
; variant.


; Example 1: to provide a set of implementations to be selected on the basis of
; the oldest required architecture
;
;  [ NoARMa
;    ; implementation suitable for ARMv2 or later
;  |
;  [ NoARMv3
;    ; implementation suitable for ARMv2a or later
;  |
;  [ NoARMv4
;    ; implementation suitable for ARMv3 or later
;  |
;    ; implementation suitable for ARMv4 or later
;  ]
;  ]
;  ]

; Example 2: to bracket an implementation suitable for ARMv2 to v4 but not v5
; onwards - for example because it stores flags in bits 0 and 1 of PC addresses
; on the stack
;
;  [ :LNOT: SupportARMv5
;    ; insert code here
;  |
;    ! 1, "No suitable implementation for required architecture(s) yet"
;  ]

; Example 3: to bracket an implementation only suitable for v4T and v5 -
; for example because it uses fine (1K) page tables
;
;  [ SupportARMv6 :LOR: NoARMT
;    ; Build targets include pre-v4T and/or v6-or-later
;    ! 1, "No suitable implementation for required architecture(s) yet"
;  |
;    ; insert code here
;  ]

; Example 4: change from SVC mode to IRQ mode in the minimal number of
; instructions for the required architecture(s)
;
;  [ :LNOT: SupportARMv3
;    ; Can only be executed in 26-bit mode
;    TEQP    PC, #2
;    NOP
;  |
;  [ NoARMG
;    ; Could be either 26-bit mode or 32-bit mode
;    TEQ     PC, PC
;    MSREQ   CPSR_c, #&12
;    TEQNEP  PC, #2
;    NOP
;  |
;    ; Can only be executed in 32-bit mode
;    MSR     CPSR_c, #&12
;  ]
;  ]

; Example 5: load a word from address in r0, which may be non-word-aligned,
; into r1. Registers r0, r2 and r3 may be corrupted.
;
; Under ARMv6, unaligned behaviour can be configured either way, but since
; ARMv7 mandates the new behaviour we have to handle it anyway, so we may as
; well run ARMv6 CPUs in ARMv7 mode.
;
;  [ :LNOT: NoARMv6
;         ; Only has to operate on CPUs with automatic unaligned LDR
;         LDR     r1,[r0]
;  |
;         ANDS    r3,r0,#3
;    [ SupportARMv6
;         ; Need to handle both CPU types at run time
;         BICNE   r0,r0,#3
;    |
;         ; Only has to operate on CPUs with traditional ARM LDM behaviour
;         ; where the bottom two bits of r0 are ignored
;    ]
;         LDMNEIA r0!,{r1,r2}
;         MOVNE   r3,r3,LSL #3
;         LDREQ   r1,[r0]
;         MOVNE   r1,r1,LSR r3
;         RSBNE   r3,r3,#32
;         ORRNE   r1,r1,r2,LSL r3
;  ]


OldOpt  SETA    {OPT}
        OPT     OptNoList+OptNoP1List

 [ :LNOT: :DEF: Included_Hdr_CPU_Arch
        GBLL    Included_Hdr_CPU_Arch
Included_Hdr_CPU_Arch SETL {TRUE}

 [ :LNOT: :DEF: Included_Hdr_Machine_Machine
        GET     Hdr:Machine.<Machine>
 ]

; MRS/MSR and USR32, IRQ32, FIQ32, SVC32, ABT and UND modes
MchFlg_v3   * 2_00000000000000000000000000000001
; LDRH/STRH, LDRSB/H, SYS mode
MchFlg_v4   * 2_00000000000000000000000000000010
; CLZ, BLX, BKPT, LDC2, STC2, CDP2, MCR2, MRC2
MchFlg_v5   * 2_00000000000000000000000000000100
; LDREX/STREX, cross-mode exception save/restore, endian-switching, packed byte
; and halfword add/subtract/absolute/saturate/halve/pack/extract,
; sign-extension, saturation, 32+32+32*32, 32+16*16+16*16, 64+16*16+16*16 and
; MSW 32*32 MLA, MLS and MUL, MCRR2, MRRC2
MchFlg_v6   * 2_00000000000000000000000000001000
; DBG, DMB, PLI, PLDW and ThumbEE instruction set
MchFlg_v7   * 2_00000000000000000000000000010000
; CRC32, HLT, LDA(EX), SEVL, STL(EX), VMAXNM, VMINNM, VRINT, VSEL
MchFlg_v8   * 2_00000000000000000000000000100000
; SWP and SWPB
MchFlg_a    * 2_00000000000000000000000001000000
; Hardware FPA - FPA10 if v2 (ARM3); FPA11 if v3 (ARM700 or ARM7500FE)
MchFlg_F    * 2_00000000000000000000000010000000
; Withdrawal of 26-bit modes
MchFlg_G    * 2_00000000000000000000000100000000
; 64+32x32 bit MLA and MUL
MchFlg_M    * 2_00000000000000000000001000000000
; BX and Thumb - Thumbv1 if ARMv4; Thumbv2 if ARMv5; Thumbv3 if ARMv6
; no established terminology for later revisions
MchFlg_T    * 2_00000000000000000000010000000000
; Enhanced DSP extension - 32+16*16, 33+32*16, 64+16*16 MLA and MUL,
; saturated ADD/SUB
MchFlg_E    * 2_00000000000000000000100000000000
; PLD, LDRD/STRD, MRRC/MCRR
MchFlg_P    * 2_00000000000000000001000000000000
; Intel XScale extensions - 40+32*32, 40+16*16, 40+16*16+16*16 MLA,
; mini data cache
MchFlg_X    * 2_00000000000000000010000000000000
; Jazelle extension - BXJ
MchFlg_J    * 2_00000000000000000100000000000000
; Multiprocessing extensions - CLREX, YIELD, WFE, WFI, SEV, SMI and
; security extensions
MchFlg_K    * 2_00000000000000001000000000000000
; Thumb 2 and more - MOVW, MOVH, bitfield operations, DSB, ISB,
; 8/16/64 bit LDR/STREX, LDRT/STRT for halfwords and signed bytes, 32-32*32 MLS
MchFlg_T2   * 2_00000000000000010000000000000000
; Virtualisation extension - ERET, HVC, banked MRS and MSR and hardware divide
MchFlg_VE   * 2_00000000000000100000000000000000
; Cryptographic extension - AES, SHA1, SHA256
MchFlg_C    * 2_00000000000001000000000000000000
; VFP - VFPv1 if ARMv5T; VFPv2 if ARMv5TE or ARMv6; VFPv3 if ARMv7
MchFlg_V    * 2_00000000000010000000000000000000
; VFP D variant (double precision)
MchFlg_VD   * 2_00000000000100000000000000000000
; VFP 32 double-precision registers variant
MchFlg_V32  * 2_00000000001000000000000000000000
; VFP half-precision variant
MchFlg_VH   * 2_00000000010000000000000000000000
; VFPv4 - fused multiply-accumulate
MchFlg_Vv4  * 2_00000000100000000000000000000000
; Advanced SIMD extensions - integer only if no VFP; FP half or single
; precision options mirror the VFP options
MchFlg_A     * 2_00000010000000000000000000000000
; Remaining flags reserved for future use
;MchFlg_     * 2_00000100000000000000000000000000
;MchFlg_     * 2_00001000000000000000000000000000
;MchFlg_     * 2_00010000000000000000000000000000
;MchFlg_     * 2_00100000000000000000000000000000
;MchFlg_     * 2_01000000000000000000000000000000
;MchFlg_     * 2_10000000000000000000000000000000

; Common flag combinations, to make the ArchitectureOption macro smaller
MchFlgs_v3   * 0            :OR: MchFlg_v3 :OR: MchFlg_a
MchFlgs_v4   * MchFlgs_v3   :OR: MchFlg_v4 :OR: MchFlg_M
MchFlgs_v4T  * MchFlgs_v4   :OR: MchFlg_G  :OR: MchFlg_T
MchFlgs_v5T  * MchFlgs_v4T  :OR: MchFlg_v5
MchFlgs_v5TE * MchFlgs_v5T  :OR: MchFlg_E  :OR: MchFlg_P
MchFlgs_v6   * MchFlgs_v5TE :OR: MchFlg_v6 :OR: MchFlg_J
MchFlgs_v7   * MchFlgs_v6   :OR: MchFlg_v7 :OR: MchFlg_K :OR: MchFlg_T2
MchFlgs_v8   * (MchFlgs_v7 :AND: :NOT: MchFlg_a) :OR: MchFlg_v8 :OR: MchFlg_VE :OR: MchFlg_V :OR: MchFlg_VD :OR: MchFlg_V32 :OR: MchFlg_VH :OR: MchFlg_Vv4 :OR: MchFlg_A

        GBLA    MchFlgs_Cumulative
MchFlgs_Cumulative    SETA 0
        GBLA    MchFlgs_CumulativeNOT
MchFlgs_CumulativeNOT SETA 0

        MACRO
$lab    ArchitectureOption $arch
        LCLA MchFlgs
 [ "$arch" = "v2"
MchFlgs SETA 0
 ELIF "$arch" = "v2a"
MchFlgs SETA MchFlg_a
 ELIF "$arch" = "v2a_FPA"
MchFlgs SETA MchFlg_a :OR: MchFlg_F
 ELIF "$arch" = "v3"
MchFlgs SETA MchFlgs_v3
 ELIF "$arch" = "v3_FPA"
MchFlgs SETA MchFlgs_v3 :OR: MchFlg_F
 ELIF "$arch" = "v3G"
MchFlgs SETA MchFlgs_v3 :OR: MchFlg_G
 ELIF "$arch" = "v3M"
MchFlgs SETA MchFlgs_v3 :OR: MchFlg_M
 ELIF "$arch" = "v4xM"
MchFlgs SETA MchFlgs_v4 :AND: :NOT: MchFlg_M
 ELIF "$arch" = "v4"
MchFlgs SETA MchFlgs_v4
 ELIF "$arch" = "v4TxM"
MchFlgs SETA MchFlgs_v4T :AND: :NOT: MchFlg_M
 ELIF "$arch" = "v4T"
MchFlgs SETA MchFlgs_v4T
 ELIF "$arch" = "v5xM"
MchFlgs SETA MchFlgs_v5T :AND: :NOT: (MchFlg_M :OR: MchFlg_T)
 ELIF "$arch" = "v5"
MchFlgs SETA MchFlgs_v5T :AND: :NOT: MchFlg_T
 ELIF "$arch" = "v5TxM"
MchFlgs SETA MchFlgs_v5T :AND: :NOT: MchFlg_M
 ELIF "$arch" = "v5T"
MchFlgs SETA MchFlgs_v5T
 ELIF "$arch" = "v5T_VFP1"
MchFlgs SETA MchFlgs_v5T :OR: MchFlg_V
 ELIF "$arch" = "v5T_VFP1D"
MchFlgs SETA MchFlgs_v5T :OR: MchFlg_V :OR: MchFlg_VD
 ELIF "$arch" = "v5TExP"
MchFlgs SETA MchFlgs_v5TE :AND: :NOT: MchFlg_P
 ELIF "$arch" = "v5TE"
MchFlgs SETA MchFlgs_v5TE
 ELIF "$arch" = "v5TEX"
MchFlgs SETA MchFlgs_v5TE :OR: MchFlg_X
 ELIF "$arch" = "v5TE_VFP2"
MchFlgs SETA MchFlgs_v5TE :OR: MchFlg_V
 ELIF "$arch" = "v5TE_VFP2D"
MchFlgs SETA MchFlgs_v5TE :OR: MchFlg_V :OR: MchFlg_VD
 ELIF "$arch" = "v5TEJ"
MchFlgs SETA MchFlgs_v5TE :OR: MchFlg_J
 ELIF "$arch" = "v5TEJ_VFP2"
MchFlgs SETA MchFlgs_v5TE :OR: MchFlg_J :OR: MchFlg_V
 ELIF "$arch" = "v5TEJ_VFP2D"
MchFlgs SETA MchFlgs_v5TE :OR: MchFlg_J :OR: MchFlg_V :OR: MchFlg_VD
 ELIF "$arch" = "v6"
MchFlgs SETA MchFlgs_v6
 ELIF "$arch" = "v6_VFP2"
MchFlgs SETA MchFlgs_v6 :OR: MchFlg_V
 ELIF "$arch" = "v6_VFP2D"
MchFlgs SETA MchFlgs_v6 :OR: MchFlg_V :OR: MchFlg_VD
 ELIF "$arch" = "v6K"
MchFlgs SETA MchFlgs_v6 :OR: MchFlg_K
 ELIF "$arch" = "v6K_VFP2"
MchFlgs SETA MchFlgs_v6 :OR: MchFlg_K :OR: MchFlg_V
 ELIF "$arch" = "v6K_VFP2D"
MchFlgs SETA MchFlgs_v6 :OR: MchFlg_K :OR: MchFlg_V :OR: MchFlg_VD
 ELIF "$arch" = "v6T2"
MchFlgs SETA MchFlgs_v6 :OR: MchFlg_T2
 ELIF "$arch" = "v6T2_VFP2"
MchFlgs SETA MchFlgs_v6 :OR: MchFlg_T2 :OR: MchFlg_V
 ELIF "$arch" = "v6T2_VFP2D"
MchFlgs SETA MchFlgs_v6 :OR: MchFlg_T2 :OR: MchFlg_V :OR: MchFlg_VD
 ELIF "$arch" = "v7"
MchFlgs SETA MchFlgs_v7
 ELIF "$arch" = "v7_VFP3"
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V
 ELIF "$arch" = "v7_VFP3D"
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VD
 ELIF "$arch" = "v7_VFP3D32"
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VD :OR: MchFlg_V32
 ELIF "$arch" = "v7_VFP3H"
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VH
 ELIF "$arch" = "v7_VFP3DH"
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VD :OR: MchFlg_VH
 ELIF "$arch" = "v7_VFP3D32H"
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VD :OR: MchFlg_V32 :OR: MchFlg_VH
 ELIF "$arch" = "v7_SIMD"
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_A
 ELIF "$arch" = "v7_VFP3_SIMD"
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_A
 ELIF "$arch" = "v7_VFP3D32_SIMD"
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VD :OR: MchFlg_V32 :OR: MchFlg_A
 ELIF "$arch" = "v7_VFP3H_SIMD"
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VH :OR: MchFlg_A
 ELIF "$arch" = "v7_VFP3D32H_SIMD"
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VD :OR: MchFlg_V32 :OR: MchFlg_VH :OR: MchFlg_A
 ELIF "$arch" = "v7VE_VFP4D32_SIMD"
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_VE :OR: MchFlg_V :OR: MchFlg_VD :OR: MchFlg_V32 :OR: MchFlg_VH :OR: MchFlg_Vv4 :OR: MchFlg_A
 ELIF "$arch" = "v8"
MchFlgs SETA MchFlgs_v8
 ELIF "$arch" = "v8_crypto"
MchFlgs SETA MchFlgs_v8 :OR: MchFlg_C
 |
   ! 1, "Unrecognised architecture: $arch"
 ]
MchFlgs_Cumulative    SETA MchFlgs_Cumulative    :OR: MchFlgs
MchFlgs_CumulativeNOT SETA MchFlgs_CumulativeNOT :OR: :NOT: MchFlgs
        MEND

      [ "$Machine" = "Archimedes" ; pre-IOMD Acorn machines, 26-bit only
        ArchitectureOption v2
        ArchitectureOption v2a
        ArchitectureOption v2a_FPA
      ELIF "$Machine" = "26" ; All 26-bit capable machines, running in 26-bit mode
        ArchitectureOption v2
        ArchitectureOption v2a
        ArchitectureOption v2a_FPA
        ArchitectureOption v3
        ArchitectureOption v3_FPA
        ArchitectureOption v4
      ELIF "$Machine" = "32" ; basic 32-bit capable machines (used for many ARM7TDMI and ARM9 ports)
        ArchitectureOption v3
        ArchitectureOption v3_FPA
        ArchitectureOption v4
        ArchitectureOption v4T
      ELIF "$Machine" = "IOMD" ; 32-bit IOMD-class machines ARM6/ARM7/StrongARM
        ArchitectureOption v3
        ArchitectureOption v3_FPA
        ArchitectureOption v4
      ELIF "$Machine" = "Tungsten" ; Iyonix PC
        ArchitectureOption v5TEX
      ELIF "$Machine" = "ARM11ZF"
        ArchitectureOption v6K_VFP2D
      ELIF "$Machine" = "RPi" ; Raspberry Pi versions are similar enough that one ROM can handle three architectures
        ArchitectureOption v6K_VFP2D
        ArchitectureOption v7VE_VFP4D32_SIMD
        ArchitectureOption v8
      ELIF "$Machine" = "CortexA7" ; Cortex A7, A15 or A17, e.g. BCM2836, TI OMAP543x, TI AM5728
        ArchitectureOption v7VE_VFP4D32_SIMD
      ELIF "$Machine" = "CortexA8" ; Cortex A8, e.g. TI OMAP35xx
        ArchitectureOption v7_VFP3D32_SIMD
      ELIF "$Machine" = "CortexA9" ; Cortex A9, e.g. TI OMAP44xx, Freescale i.MX6
        ArchitectureOption v7_VFP3D32H_SIMD
      ELIF "$Machine" = "CortexA53" ; Cortex A53, A57, A35, A72 or A73, e.g. Allwinner A64, Broadcom BCM2837, Rockchip RK3399
        ArchitectureOption v8_crypto
      ELIF "$Machine" = "All" ; if the target code is required to run on
                           ; any RISC OS machine
        ArchitectureOption v2
        ArchitectureOption v2a_FPA
        ArchitectureOption v8
      ELIF "$Machine" = "All32" ; if the target code is required to run on
                             ; any 32-bit capable RISC OS machine
        ArchitectureOption v3
        ArchitectureOption v3_FPA
        ArchitectureOption v8
      |
        ! 1, "Unrecognised machine: $Machine"
      ]

        GBLL    SupportARMv3
SupportARMv3 SETL  (MchFlgs_Cumulative :AND: MchFlg_v3) > 0
        GBLL    NoARMv3
NoARMv3 SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_v3) > 0

        GBLL    SupportARMv4
SupportARMv4 SETL  (MchFlgs_Cumulative :AND: MchFlg_v4) > 0
        GBLL    NoARMv4
NoARMv4 SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_v4) > 0

        GBLL    SupportARMv5
SupportARMv5 SETL  (MchFlgs_Cumulative :AND: MchFlg_v5) > 0
        GBLL    NoARMv5
NoARMv5 SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_v5) > 0

        GBLL    SupportARMv6
SupportARMv6 SETL  (MchFlgs_Cumulative :AND: MchFlg_v6) > 0
        GBLL    NoARMv6
NoARMv6 SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_v6) > 0

        GBLL    SupportARMv7
SupportARMv7 SETL  (MchFlgs_Cumulative :AND: MchFlg_v7) > 0
        GBLL    NoARMv7
NoARMv7 SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_v7) > 0

        GBLL    SupportARMv8
SupportARMv8 SETL  (MchFlgs_Cumulative :AND: MchFlg_v8) > 0
        GBLL    NoARMv8
NoARMv8 SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_v8) > 0

        GBLL    SupportARMa
SupportARMa SETL   (MchFlgs_Cumulative :AND: MchFlg_a) > 0
        GBLL    NoARMa
NoARMa  SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_a) > 0

        GBLL    SupportARMF
SupportARMF SETL   (MchFlgs_Cumulative :AND: MchFlg_F) > 0
        GBLL    NoARMF
NoARMF  SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_F) > 0

        GBLL    SupportARMG
SupportARMG SETL   (MchFlgs_Cumulative :AND: MchFlg_G) > 0
        GBLL    NoARMG
NoARMG  SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_G) > 0

        GBLL    SupportARMM
SupportARMM SETL   (MchFlgs_Cumulative :AND: MchFlg_M) > 0
        GBLL    NoARMM
NoARMM  SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_M) > 0

        GBLL    SupportARMT
SupportARMT SETL   (MchFlgs_Cumulative :AND: MchFlg_T) > 0
        GBLL    NoARMT
NoARMT  SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_T) > 0

        GBLL    SupportARME
SupportARME SETL   (MchFlgs_Cumulative :AND: MchFlg_E) > 0
        GBLL    NoARME
NoARME  SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_E) > 0

        GBLL    SupportARMP
SupportARMP SETL   (MchFlgs_Cumulative :AND: MchFlg_P) > 0
        GBLL    NoARMP
NoARMP  SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_P) > 0

        GBLL    SupportARMX
SupportARMX SETL   (MchFlgs_Cumulative :AND: MchFlg_X) > 0
        GBLL    NoARMX
NoARMX  SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_X) > 0

        GBLL    SupportARMJ
SupportARMJ SETL   (MchFlgs_Cumulative :AND: MchFlg_J) > 0
        GBLL    NoARMJ
NoARMJ  SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_J) > 0

        GBLL    SupportARMK
SupportARMK SETL   (MchFlgs_Cumulative :AND: MchFlg_K) > 0
        GBLL    NoARMK
NoARMK  SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_K) > 0

        GBLL    SupportARMT2
SupportARMT2 SETL  (MchFlgs_Cumulative :AND: MchFlg_T2) > 0
        GBLL    NoARMT2
NoARMT2 SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_T2) > 0

        GBLL    SupportARMVE
SupportARMVE SETL  (MchFlgs_Cumulative :AND: MchFlg_VE) > 0
        GBLL    NoARMVE
NoARMVE SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_VE) > 0

        GBLL    SupportARMC
SupportARMC SETL   (MchFlgs_Cumulative :AND: MchFlg_C) > 0
        GBLL    NoARMC
NoARMC  SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_C) > 0

        GBLL    SupportARMV
SupportARMV SETL   (MchFlgs_Cumulative :AND: MchFlg_V) > 0
        GBLL    NoARMV
NoARMV  SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_V) > 0

        GBLL    SupportARMVD
SupportARMVD SETL  (MchFlgs_Cumulative :AND: MchFlg_VD) > 0
        GBLL    NoARMVD
NoARMVD SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_VD) > 0

        GBLL    SupportARMV32
SupportARMV32 SETL (MchFlgs_Cumulative :AND: MchFlg_V32) > 0
        GBLL    NoARMV32
NoARMV32 SETL   (MchFlgs_CumulativeNOT :AND: MchFlg_V32) > 0

        GBLL    SupportARMVH
SupportARMVH SETL  (MchFlgs_Cumulative :AND: MchFlg_VH) > 0
        GBLL    NoARMVH
NoARMVH SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_VH) > 0

        GBLL    SupportARMVv4
SupportARMVv4 SETL  (MchFlgs_Cumulative :AND: MchFlg_Vv4) > 0
        GBLL    NoARMVv4
NoARMVv4 SETL   (MchFlgs_CumulativeNOT :AND: MchFlg_Vv4) > 0

        GBLL    SupportARMA
SupportARMA SETL   (MchFlgs_Cumulative :AND: MchFlg_A) > 0
        GBLL    NoARMA
NoARMA  SETL    (MchFlgs_CumulativeNOT :AND: MchFlg_A) > 0

 ]

        OPT     OldOpt
        END
