; Copyright 1996 Acorn Computers Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
;     http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
        SUBT    Definition of IO common across all platforms ==> Hdr:IO.GenericIO

OldOpt  SETA    {OPT}
        OPT     OptNoList+OptNoP1List

; ***********************************
; ***    C h a n g e   L i s t    ***
; ***********************************
;
; Date       Name          Description
; ----       ----          -----------
; 04-Jan-93  JRoach        Created from Hdr:IO.IOC
;
; Note this file defines the stuff common across all IOC implementations
;

; Yes, believe it or not, 'IOC' has to stay fixed in location
;
IOC             EQU     &03200000                       ; Hardware specific address

        ; IOC register offsets

IOCControl      EQU     &00             ; Control register

IOCSERTX        EQU     &04             ; Serial TX
IOCSERRX        EQU     &04             ;        RX

IOCIRQSTAA      EQU     &10             ; IRQ A Status
IOCIRQREQA      EQU     &14             ;       Requesting
IOCIRQCLRA      EQU     &14             ;       Clear
IOCIRQMSKA      EQU     &18             ;       Mask

IOCIRQSTAB      EQU     &20             ; IRQ B Status
IOCIRQREQB      EQU     &24             ;       Requesting
IOCIRQCLRB      EQU     &24             ;       Clear
IOCIRQMSKB      EQU     &28             ;       Mask

IOCFIQSTA       EQU     &30             ; FIQ   Status
IOCFIQREQ       EQU     &34             ;       Requesting
IOCFIQMSK       EQU     &38             ;       Mask

Timer0LL        EQU     &40             ; Timer 0 Write low input latch
Timer0LH        EQU     &44             ;         Write high input latch
Timer0GO        EQU     &48             ;         Load count from input latch
Timer0CL        EQU     &40             ;         Read low output latch
Timer0CH        EQU     &44             ;         Read high output latch
Timer0LR        EQU     &4C             ;         Load output latch from count

Timer1LL        EQU     &50             ; Timer 1 Write low input latch
Timer1LH        EQU     &54             ;         Write high input latch
Timer1GO        EQU     &58             ;         Load count from input latch
Timer1CL        EQU     &50             ;         Read low output latch
Timer1CH        EQU     &54             ;         Read high output latch
Timer1LR        EQU     &5C             ;         Load output latch from count

; Timer2 and Timer3 aren't in the generic IOC

        ; IOC register addresses

                ^       IOC

IOC_Control     #       &04             ; Control register

IOC_SERTX       #       &00             ; Serial TX
IOC_SERRX       #       &0C             ;        RX

IOC_IRQSTAA     #       &04             ; IRQ A Status
IOC_IRQREQA     #       &00             ;       Requesting
IOC_IRQCLRA     #       &04             ;       Clear
IOC_IRQMSKA     #       &08             ;       Mask

IOC_IRQSTAB     #       &04             ; IRQ B Status
IOC_IRQREQB     #       &00             ;       Requesting
IOC_IRQCLRB     #       &04             ;       Clear
IOC_IRQMSKB     #       &08             ;       Mask

IOC_FIQSTA      #       &04             ; FIQ   Status
IOC_FIQREQ      #       &04             ;       Requesting
IOC_FIQMSK      #       &08             ;       Mask

IOC_Timer0LL    #       &00             ; Timer 0 Write low input latch
IOC_Timer0CL    #       &04             ;         Read low output latch
IOC_Timer0LH    #       &00             ;         Write high input latch
IOC_Timer0CH    #       &04             ;         Read high output latch
IOC_Timer0GO    #       &04             ;         Load count from input latch
IOC_Timer0LR    #       &04             ;         Load output latch from count

IOC_Timer1LL    #       &00             ; Timer 1 Write low input latch
IOC_Timer1CL    #       &04             ;         Read low output latch
IOC_Timer1LH    #       &00             ;         Write high input latch
IOC_Timer1CH    #       &04             ;         Read high output latch
IOC_Timer1GO    #       &04             ;         Load count from input latch
IOC_Timer1LR    #       &04             ;         Load output latch from count

; Generic IOC doesn't have Timer2 and Timer3

; Now we'll define the fixed bits in the IRQ masks


        ; Control register bits

i2c_clock_bit                   * 1 :SHL: 1  ; Read/Write
i2c_data_bit                    * 1 :SHL: 0  ; Read/Write
IOEB_ID_bit_number              * 3
IOEB_unique_machine_ID_bit      * 1 :SHL: IOEB_ID_bit_number ; Dallas DS2400 unique machine ID chip control line


        ; IRQ register A bits

force_bit               * 1 :SHL: 7  ; Force Interrupt       (FIQ owned)
timer1_bit              * 1 :SHL: 6  ; Timer 1 crossing zero (event)
timer0_bit              * 1 :SHL: 5  ; Timer 0 crossing zero (event)
por_bit                 * 1 :SHL: 4  ; Power on RESET flag   (event)
vsync_bit               * 1 :SHL: 3  ; VFLYBK starting       (event)  IR
; bit 2 varies from machine to machine
; bit 1 varies from machine to machine
; bit 0 varies from machine to machine


        ; IRQ register B bits

serial_Rx_bit           * 1 :SHL: 7  ; Keyboard recieve full
serial_Tx_bit           * 1 :SHL: 6  ; Keyboard transmit empty
podule_IRQ_bit          * 1 :SHL: 5  ; Podule IRQ request
; bit 4 varies from machine to machine
; bit 3 varies from machine to machine
; bit 2 varies from machine to machine
; bit 1 varies from machine to machine
podule_FIQ_as_IRQ_bit   * 1 :SHL: 0 ; Podule FIQ causing IRQ


        ; FIQ register bits

podule_FIQ_bit  * 1 :SHL: 6                             ; Podule FIQ request
floppy_DMA_bit  * 1 :SHL: 0                             ; floppy FIQ for DMA

; 'Generic' VIDC stuff, sort of

ClockControlShift * 9           ; LSbit of clock control bits
                                ; as specified in internal VIDC CR format

ClockControlMask * 3 :SHL: ClockControlShift ; 2 bits of clock control

SyncControlShift * 11           ; LSbit of sync polarity control bits
                                ; as specified in internal VIDC CR format

SyncControlMask * 3 :SHL: SyncControlShift ; 2 bits of sync polarity control

; Generic IO locations
IOEB_ASICPresent        * &03350050
LC_ASICPresent          * &0302C03C

        OPT     OldOpt
        END
