; Copyright 1996 Acorn Computers Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
;     http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
        SUBT    Specific definition of IOC ==> Hdr:IO.IOC

OldOpt  SETA    {OPT}
        OPT     OptNoList+OptNoP1List

; ***********************************
; ***    C h a n g e   L i s t    ***
; ***********************************
;
; Date       Name          Description
; ----       ----          -----------
; 04-Jan-93  BCockburn     Created from Hdr:System
; 13-Jul-93  JRoach        Moved the generic stuff to Hdr:IO.GenericIOC
;
; This defines the registers specific to 86C410 implmementations of IOC.
; This chip is more often referred to as IOC.
;

 [ :LNOT: :DEF: IOC_HDR_INCLUDED
        GBLL    IOC_HDR_INCLUDED

        ; IOC register offsets

Timer2LL        EQU     &60             ; Timer 2 Write low input latch
Timer2LH        EQU     &64             ;         Write high input latch
Timer2GO        EQU     &68             ;         Load count from input latch
Timer2CL        EQU     &60             ;         Read low output latch
Timer2CH        EQU     &64             ;         Read high output latch
Timer2LR        EQU     &6C             ;         Load output latch from count

Timer3LL        EQU     &70             ; Timer 3 Write low input latch
Timer3LH        EQU     &74             ;         Write high input latch
Timer3GO        EQU     &78             ;         Load count from input latch
Timer3CL        EQU     &70             ;         Read low output latch
Timer3CH        EQU     &74             ;         Read high output latch
Timer3LR        EQU     &7C             ;         Load output latch from count

        ; IOC register addresses

                ^       IOC
                #       &60

IOC_Timer2LL    #       &00             ; Timer 2 Write low input latch
IOC_Timer2CL    #       &04             ;         Read low output latch
IOC_Timer2LH    #       &00             ;         Write high input latch
IOC_Timer2CH    #       &04             ;         Read high output latch
IOC_Timer2GO    #       &04             ;         Load count from input latch
IOC_Timer2LR    #       &04             ;         Load output latch from count

IOC_Timer3LL    #       &00             ; Timer 3 Write low input latch
IOC_Timer3CL    #       &04             ;         Read low output latch
IOC_Timer3LH    #       &00             ;         Write high input latch
IOC_Timer3CH    #       &04             ;         Read high output latch
IOC_Timer3GO    #       &04             ;         Load count from input latch
IOC_Timer3LR    #       &04             ;         Load output latch from count

IOEB_LatchB         * &03350018 ; Fast, Bank 5
LatchB              * &03350018 ; Fast, Bank 5
VIDCClockSelect * &03350048     ; bits 0 and 1 control speed, as follows:-
                                ; 0 => 24 MHz
                                ; 1 => 25.175 MHz
                                ; 2 => 36 MHz
                                ; 3 => do not use
IOEB_MonitorType    * &03350070
 ]

        OPT     OldOpt
        END
