; Copyright 1996 Acorn Computers Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
;     http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
        SUBT    Definition of the A400 production platform ==> Hdr:IO.A440

OldOpt  SETA    {OPT}
        OPT     OptNoList+OptNoP1List

; ***********************************
; ***    C h a n g e   L i s t    ***
; ***********************************
;
; Date       Name          Description
; ----       ----          -----------
; 13-Jul-93  JRoach        Created

        GET     Hdr:IO.IOC

        ; Control register bits

IOEB_sound_mute_bit             * 1 :SHL: 5             ; Read/Write
IOEB_serial_FIQ_bits            * 1 :SHL: 4             ; Must only write a "1"
IOEB_floppy_density_bit         * 1 :SHL: 2             ; ???
                                                        ; (used to be reset disable bit)

        ; IRQ register A bits

IOEB_floppy_index_bit           * 1 :SHL: 2             ; Set at start of index
IOEB_battery_low_bit            * 1 :SHL: 1             ; Was rining on A1
pbusy_bit                       * 1 :SHL: 0             ; Printer busy          (level)


        ; IRQ register B bits

IOEB_ide_IRQ_bit                * 1 :SHL: 4
IOEB_floppy_IRQ_bit             * 1 :SHL: 3
serial_bit                      * 1 :SHL: 2
IOEB_sound_IRQ_bit              * 1 :SHL: 1             ; sound buffer reload


        ; FIQ register bits

IOEB_econet_bit                 * 1 :SHL: 2
IOEB_serial_FIQ_bit             * 1 :SHL: 4             ; also IRQ reg 'B'




        ; IO device locations
C710                    * &03010000
LC_Base                 * &0302C000
IOEB_LatchA             * &03350040 ; Fast, Bank 5
IOEB_ProcessorSpeed     * &03350054
IOEB_SoundSuppress      * &03350074
PINTR_Latch             * &03350558 ; r/w to clear ACK from parallel (via PAL)
IOEB_EconetController   * &033A0000 ; Sync, Bank 2

        ; LC ASIC registers

        ^       0

LC_VDSR_lo      #       4
LC_VDSR_mid     #       4
LC_VDSR_hi      #       4
LC_VDLR_lo      #       4

LC_VDLR_mid     #       4
LC_VDLR_hi      #       4
LC_HDSR_lo      #       4
LC_HDSR_mid     #       4

LC_HDSR_hi      #       4
LC_HDLR_lo      #       4
LC_HDLR_mid     #       4
LC_HDLR_hi      #       4

LC_LICR_lo      #       4
LC_LICR_mid     #       4
LC_LICR_hi      #       4
LC_Reset        #       4
        ASSERT LC_ASICPresent = LC_Base + LC_Reset

LC_PaletteOffset #      16*4

; Some bits in those registers

LC_LICR_lo_EconetEnable *       1 :SHL: 0
LC_LICR_lo_LCDEnable    *       1 :SHL: 1
LC_LICR_lo_VideoEnable  *       1 :SHL: 2
LC_LICR_lo_SerialEnable *       1 :SHL: 3

LC_LICR_mid_DualEnable  *       1 :SHL: 0
LC_LICR_mid_ClockBits   *       3 :SHL: 1       ; control which clock is fed to VIDC
LC_LICR_mid_ExtClock    *       0 :SHL: 1       ; use external clock (from IOEB)
LC_LICR_mid_Crys2Clock  *       1 :SHL: 1       ; use crystal clock divided by 2
LC_LICR_mid_CrysClock   *       2 :SHL: 1       ; use crystal clock
LC_LICR_mid_InvertClock *       1 :SHL: 3

LC_LICR_hi_BacklightEnable *    1 :SHL: 0
LC_LICR_hi_ExtraLines1  *       0 :SHL: 1
LC_LICR_hi_ExtraLines2  *       1 :SHL: 1
LC_LICR_hi_DRAMs1       *       0 :SHL: 2
LC_LICR_hi_DRAMs2       *       1 :SHL: 2

LC_Reset_Hold           *       1 :SHL: 0
LC_Reset_SoftwareReset  *       1 :SHL: 1       ; not normally needed


        OPT     OldOpt
        END
