; Copyright 1996 Acorn Computers Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
;     http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
; > Hdr:IOMD

; ********************
; *** Changes List ***
; ********************

; 10-Dec-92 TMD Created.
; 24-Feb-93 TMD Updated for DRAM-video-capable IOMD.
; 23-Mar-93 TMD Added burst mode bits to ROMCR.
; 23-Apr-93 TMD Added IOMD_MonitorType, IOMD_MonitorIDMask
; 25-May-93 MT  Added extra definitions for DMA registers
; 24-Jun-93 TMD Replaced references to SCSI by Network
; 30-Jun-93 TMD Changed IOMD_Network_IRQ_bit to IOMD_HardDisc_IRQ_bit and
;                       IOMD_ext_IRQ_bit to IOMD_Network_IRQ_bit
; 09-Aug-93 SMC Added base addresses for EASI space.
; 19-Oct-93 TMD Added IOMD_ProtectionLinkBit
; 06-May-94 RCM Added extra registers provided by MORRIS
; 13-Jun-94 RCM Added more MORRIS bits
; 22-Nov-94 RCM Added more MORRIS bits
; 08-Mar-95 RCM Added IOMD_VIDMUX
; 08-Mar-95 RCM Added IOMD_SoundsystemLinkBit
; 06-Feb-96 SMC Added Morris IRQC registers
; 15-May-96 BAR Added 'Half' spped clock prescaler variables.
; 17-Jun-96 BAR Added IOMD ID Version numbers.
; 09-Jul-96 BAR Added New constants for ROM speed selection.
; 11-Jul-96 TMD Added ASTCR and new DRAMWID bits
; ---------
; 03-Dec-96 RWB RiscOS merge project - added the following from RiscOS370 tree
;		IOMD_ATODICR, IOMD_ATODSR, IOMD_ATODCC, IOMD_ATODCNT1,
;		IOMD_ATODCNT2, IOMD_ATODCNT3, IOMD_ATODCNT4, IOMD_VIDINITB,
;		IOMD_VIDCR_Dup


 [ :LNOT: :DEF: IOMD_Base

 [ :LNOT: :DEF: MorrisSupport
                GBLL    MorrisSupport
MorrisSupport   SETL    {FALSE}
 ]

                GBLA    IOMD_Base
IOMD_Base       SETA    &03200000       ; Same address as IOC was

; Offsets within IOMD
IOMD_KBDCR      *       &008            ; Keyboard control

IOMD_CLINES     *       &00C            ; General purpose IO register with Monitor Id in bit 0

 [ MorrisSupport
IOMD_IDLEMODE   *       &01C
IOMD_STOPMODE   *       &02C
IOMD_CLKCTL     *       &03C
 ]

 [ MorrisSupport
IOMD_IRQSTC     *       &060            ; IRQ C interrupts status
IOMD_IRQRQC     *       &064            ; IRQ C interrupts request
IOMD_IRQMSKC    *       &068            ; IRQ C interrupts mask
IOMD_VIDMUX     *       &06C            ; Video LCD and Serial Sound Mux control
IOMD_IRQSTD     *       &070            ; IRQ D interrupts status
IOMD_IRQRQD     *       &074            ; IRQ D interrupts request
IOMD_IRQMSKD    *       &078            ; IRQ D interrupts mask
 ]

IOMD_ROMCR0     *       &080            ; ROM control bank 0
IOMD_ROMCR1     *       &084            ; ROM control bank 1
IOMD_DRAMCR     *       &088            ; DRAM control
IOMD_VREFCR     *       &08C            ; VRAM and refresh control
IOMD_FSIZE      *       &090            ; Flyback line size
IOMD_ID0        *       &094            ; Chip ID no. low byte
IOMD_ID1        *       &098            ; Chip ID no. high byte
IOMD_VERSION    *       &09C            ; Chip version number

IOMD_MOUSEX     *       &0A0            ; Mouse X position
IOMD_MOUSEY     *       &0A4            ; Mouse Y position

 [ MorrisSupport
IOMD_MSEDAT     *       &A8             ; Mouse data                     } 2nd PS2 channel
IOMD_MSECR      *       &AC             ; Mouse control - see IOMD_KBDCR }
 ]

IOMD_DMATCR     *       &0C0            ; DACK timing control
IOMD_IOTCR      *       &0C4            ; I/O timing control
IOMD_ECTCR      *       &0C8            ; Expansion card timing control
IOMD_DMAEXT     *       &0CC            ; DMA external control

 [ MorrisSupport
IOMD_ASTCR	*	&0CC		; I/O asynchronous timing control - same address as old DMAEXT on IOMD
IOMD_DRAMWID    *       &0D0            ; DRAM width control
IOMD_SELFREF    *       &0D4            ; DRAM Self Refresh control

IOMD_ATODICR    *       &0E0
IOMD_ATODSR     *       &0E4
IOMD_ATODCC     *       &0E8
IOMD_ATODCNT1   *       &0EC
IOMD_ATODCNT2   *       &0F0
IOMD_ATODCNT3   *       &0F4
IOMD_ATODCNT4   *       &0F8
 ]

IOMD_IO0CURA    *       &100            ; I/O DMA 0     CurA
IOMD_IO0ENDA    *       &104            ;               EndA
IOMD_IO0CURB    *       &108            ;               CurB
IOMD_IO0ENDB    *       &10C            ;               EndB
IOMD_IO0CR      *       &110            ;               Control
IOMD_IO0ST      *       &114            ;               Status

IOMD_IO1CURA    *       &120            ; I/O DMA 1     CurA
IOMD_IO1ENDA    *       &124            ;               EndA
IOMD_IO1CURB    *       &128            ;               CurB
IOMD_IO1ENDB    *       &12C            ;               EndB
IOMD_IO1CR      *       &130            ;               Control
IOMD_IO1ST      *       &134            ;               Status

IOMD_IO2CURA    *       &140            ; I/O DMA 2     CurA
IOMD_IO2ENDA    *       &144            ;               EndA
IOMD_IO2CURB    *       &148            ;               CurB
IOMD_IO2ENDB    *       &14C            ;               EndB
IOMD_IO2CR      *       &150            ;               Control
IOMD_IO2ST      *       &154            ;               Status

IOMD_IO3CURA    *       &160            ; I/O DMA 3     CurA
IOMD_IO3ENDA    *       &164            ;               EndA
IOMD_IO3CURB    *       &168            ;               CurB
IOMD_IO3ENDB    *       &16C            ;               EndB
IOMD_IO3CR      *       &170            ;               Control
IOMD_IO3ST      *       &174            ;               Status

IOMD_SD0CURA    *       &180            ; Sound DMA 0   CurA
IOMD_SD0ENDA    *       &184            ;               EndA
IOMD_SD0CURB    *       &188            ;               CurB
IOMD_SD0ENDB    *       &18C            ;               EndB
IOMD_SD0CR      *       &190            ;               Control
IOMD_SD0ST      *       &194            ;               Status

IOMD_SD1CURA    *       &1A0            ; Sound DMA 1   CurA
IOMD_SD1ENDA    *       &1A4            ;               EndA
IOMD_SD1CURB    *       &1A8            ;               CurB
IOMD_SD1ENDB    *       &1AC            ;               EndB
IOMD_SD1CR      *       &1B0            ;               Control
IOMD_SD1ST      *       &1B4            ;               Status

IOMD_CURSCUR    *       &1C0            ; Cursor DMA    Current
IOMD_CURSINIT   *       &1C4            ;               Init

IOMD_VIDCUR     *       &1D0            ; Video DMA     Current
IOMD_VIDEND     *       &1D4            ;               End
IOMD_VIDSTART   *       &1D8            ;               Start
IOMD_VIDINIT    *       &1DC            ;               Init
IOMD_VIDCR      *       &1E0            ;               Control
IOMD_VIDINITB   *       &1E8            ;               InitB (for dual-scan LCDs)

IOMD_DMASTA     *       &1F0            ; DMA Interrupt Status
IOMD_DMAREQ     *       &1F4            ;               Request
IOMD_DMAMSK     *       &1F8            ;               Mask

 [ MorrisSupport
; Bits in CLKCTL (Clock Prescaler Control)

IOMD_CLKCTL_CpuclkNormal *      1 :SHL: 2       ; 1=div1
IOMD_CLKCTL_MemclkNormal *      1 :SHL: 1       ; 1=div1
IOMD_CLKCTL_IOclkNormal  *      1 :SHL: 0       ; 1=div1

IOMD_CLKCTL_CpuclkHalf   *      0 :SHL: 2       ; 0=div2
IOMD_CLKCTL_MemclkHalf   *      0 :SHL: 1       ; 0=div2
IOMD_CLKCTL_IOclkHalf    *      0 :SHL: 0       ; 0=div2
 ]

; Bits in IOCR (I/O Control Register)

vsync_state_bit         *       1 :SHL: 7       ; read only
floppy_index_state_bit  *       1 :SHL: 6       ; read only
IOMD_unique_machine_ID_bit *    1 :SHL: 3       ; read/write

; Bits in KBDCR (Keyboard Control Register)

IOMD_KBDCR_TxE          *       1 :SHL: 7       ; Transmit register empty
IOMD_KBDCR_TxB          *       1 :SHL: 6       ; Transmit busy
IOMD_KBDCR_RxF          *       1 :SHL: 5       ; Receive register full
IOMD_KBDCR_RxB          *       1 :SHL: 4       ; Receive busy
IOMD_KBDCR_Enable       *       1 :SHL: 3       ; Enable state machine
IOMD_KBDCR_RxPar        *       1 :SHL: 2       ; Receive parity
IOMD_KBDCR_Ndata        *       1 :SHL: 1       ; NOT data
IOMD_KBDCR_Nclock       *       1 :SHL: 0       ; NOT clock

; Bits in MSECR (Mouse Control Resister (exactly the same as Keyboard Control Register))

IOMD_MSECR_TxE          *       1 :SHL: 7       ; Transmit register empty
IOMD_MSECR_TxB          *       1 :SHL: 6       ; Transmit busy
IOMD_MSECR_RxF          *       1 :SHL: 5       ; Receive register full
IOMD_MSECR_RxB          *       1 :SHL: 4       ; Receive busy
IOMD_MSECR_Enable       *       1 :SHL: 3       ; Enable state machine
IOMD_MSECR_RxPar        *       1 :SHL: 2       ; Receive parity
IOMD_MSECR_Ndata        *       1 :SHL: 1       ; NOT data
IOMD_MSECR_Nclock       *       1 :SHL: 0       ; NOT clock

; Bits in IRQ register A

IOMD_floppy_index_bit   *       1 :SHL: 2       ; Floppy index pulse    (event)

; Bits in IRQ register B

IOMD_floppy_IRQ_bit      *       1 :SHL: 4       ; Floppy IRQ request
IOMD_Network_IRQ_bit     *       1 :SHL: 3       ; Network (Extended) IRQ request
IOMD_HardDisc_IRQ_bit    *       1 :SHL: 1       ; Hard disc (IDE) IRQ

 [ MorrisSupport
; Bits in IRQ register D

IOMD_Nevent2_bit          *     1 :SHL: 4       ;
IOMD_Nevent1_bit          *     1 :SHL: 3       ;
IOMD_AtoD_IRQ_bit         *     1 :SHL: 2       ; A to D (Joystick) IRQ request
IOMD_MouseTxEmpty_IRQ_bit *     1 :SHL: 1       ; PS2 Mouse port Tx empty IRQ request
IOMD_MouseRxFull_IRQ_bit  *     1 :SHL: 0       ; PS2 Mouse port Rx full IRQ request
 ]

; Bits in FIQ register

IOMD_serial_FIQ_bit     *       1 :SHL: 4       ; Serial FIQ request
IOMD_ext_FIQ_bit        *       1 :SHL: 1       ; Extended FIQ request

; Values to store in ROM control registers (0 and 1)

IOMD_ROMCR_NSTicks_7    *       0 :SHL: 0
IOMD_ROMCR_NSTicks_6    *       1 :SHL: 0
IOMD_ROMCR_NSTicks_5    *       2 :SHL: 0
IOMD_ROMCR_NSTicks_4    *       3 :SHL: 0
IOMD_ROMCR_NSTicks_3    *       4 :SHL: 0
IOMD_ROMCR_NSTicks_2    *       5 :SHL: 0

IOMD_ROMCR_218          *       IOMD_ROMCR_NSTicks_7
IOMD_ROMCR_187          *       IOMD_ROMCR_NSTicks_6
IOMD_ROMCR_156          *       IOMD_ROMCR_NSTicks_5
IOMD_ROMCR_125          *       IOMD_ROMCR_NSTicks_4
IOMD_ROMCR_93           *       IOMD_ROMCR_NSTicks_3
IOMD_ROMCR_62           *       IOMD_ROMCR_NSTicks_2

IOMD_ROMCR_BTicks_0     *       0 :SHL: 3
IOMD_ROMCR_BTicks_4     *       1 :SHL: 3
IOMD_ROMCR_BTicks_3     *       2 :SHL: 3
IOMD_ROMCR_BTicks_2     *       3 :SHL: 3

IOMD_ROMCR_BurstOff     *       IOMD_ROMCR_BTicks_0       ; burst mode off
IOMD_ROMCR_Burst125     *       IOMD_ROMCR_BTicks_4       ; 125 ns burst
IOMD_ROMCR_Burst93      *       IOMD_ROMCR_BTicks_3       ; 93.75 ns burst
IOMD_ROMCR_Burst62      *       IOMD_ROMCR_BTicks_2       ; 62.5 ns burst

 [ MorrisSupport
IOMD_ROMCR_HalfSpeed    *       0 :SHL: 5
IOMD_ROMCR_Normal       *       1 :SHL: 5
IOMD_ROMCR_32bit        *       0 :SHL: 6
IOMD_ROMCR_16bit        *       1 :SHL: 6
 ]

; Bits in VREFCR

IOMD_VREFCR_VRAM_1Mx32          *       0 :SHL: 5
IOMD_VREFCR_VRAM_256Kx32        *       1 :SHL: 5
IOMD_VREFCR_VRAM_256Kx64        *       2 :SHL: 5
IOMD_VREFCR_VRAM_1Mx64          *       6 :SHL: 5

IOMD_VREFCR_REF_Off     *       0 :SHL: 0       ; off
IOMD_VREFCR_REF_16      *       1 :SHL: 0       ; 16s refresh
IOMD_VREFCR_REF_128     *       8 :SHL: 0       ; 128s refresh


 [ MorrisSupport
IOMD_DRAMWID_DRAM_32bit * 0 :SHL: 0             ; 32bit
IOMD_DRAMWID_DRAM_16bit * 1 :SHL: 0             ; 16bit

; The following bits are new to ARM7500FE
; Note that the ARM7500FE data sheet now refers to this register as DRAMCR
; but that name clashes with the earlier DRAMCR on IOMD

IOMD_DRAMWID_EDO_Enable * 1 :SHL: 4		; enable use of EDO DRAM

IOMD_DRAMWID_RASCAS_2   * 0 :SHL: 5		; 2 memory clock cycles from falling nRAS
						; to falling nCAS
IOMD_DRAMWID_RASCAS_3   * 1 :SHL: 5		; 3 memory clock cycles from falling nRAS
						; to falling nCAS
IOMD_DRAMWID_RASPre_3	* 0 :SHL: 6		; 3 memory clock cycles guaranteed RAS precharge
IOMD_DRAMWID_RASPre_4	* 1 :SHL: 6		; 4 memory clock cycles guaranteed RAS precharge

; Values to put in ASTCR

IOMD_ASTCR_Minimal	* 0 :SHL: 7		; minimal delay to I/O cycles
IOMD_ASTCR_WaitStates	* 1 :SHL: 7		; add wait states to cope with fast MEMCLK

 ]

; Bits in IOTCR

IOMD_IOTCR_Network_TypeA   *    0 :SHL: 0
IOMD_IOTCR_Network_TypeB   *    1 :SHL: 0
IOMD_IOTCR_Network_TypeC   *    2 :SHL: 0
IOMD_IOTCR_Network_TypeD   *    3 :SHL: 0

IOMD_IOTCR_Combo_TypeA  *       0 :SHL: 2
IOMD_IOTCR_Combo_TypeB  *       1 :SHL: 2
IOMD_IOTCR_Combo_TypeC  *       2 :SHL: 2
IOMD_IOTCR_Combo_TypeD  *       3 :SHL: 2

IOMD_IOTCR_Sound_TypeA  *       0 :SHL: 4
IOMD_IOTCR_Sound_TypeB  *       1 :SHL: 4
IOMD_IOTCR_Sound_TypeC  *       2 :SHL: 4
IOMD_IOTCR_Sound_TypeD  *       3 :SHL: 4

IOMD_IOTCR_Sound_Word   *       0 :SHL: 6
IOMD_IOTCR_Sound_Byte   *       1 :SHL: 6
IOMD_IOTCR_Sound_2Bytes *       2 :SHL: 6

; Bits in DMA end addresses

IOMD_DMA_S_Bit          *       1 :SHL: 31      ; Stop DMA (raise TC) at end of buffer
IOMD_DMA_L_Bit          *       1 :SHL: 30      ; Last (single-unit) transfer on buffer
                                                ; - also in VIDINIT, in same position

; Bits in DMA control registers
IOMD_DMA_C_Bit          *       1 :SHL: 7       ; Clear DMA channel to idle, when written as 1
IOMD_DMA_D_Bit          *       1 :SHL: 6       ; Direction: 0=mem->dev,1=dev->mem
IOMD_DMA_E_Bit          *       1 :SHL: 5       ; Enable DMA channel's state machine when set
IOMD_DMA_IncMask        *       2_00011111      ; Mask for DMA channel increment

; Bits in DMA status registers
IOMD_DMA_O_Bit          *       1 :SHL: 2       ; Overrun has occured if set
IOMD_DMA_I_Bit          *       1 :SHL: 1       ; channel is Interrupting if set
IOMD_DMA_B_Bit          *       1 :SHL: 0       ; active cur/end pair: 0=A, 1=B

; Channel bit assignments in DMA Interrupt registers IOMD_DMA{STA,MSK,REQ}
IOMD_DMA_IO0            *       1 :SHL: 0
IOMD_DMA_IO1            *       1 :SHL: 1
IOMD_DMA_IO2            *       1 :SHL: 2
IOMD_DMA_IO3            *       1 :SHL: 3
IOMD_DMA_SD0            *       1 :SHL: 4
IOMD_DMA_SD1            *       1 :SHL: 5

; Bits in VIDCR

IOMD_VIDCR_DRAMMode     *       1 :SHL: 6       ; set for DRAM, clear for VRAM
IOMD_VIDCR_Enable       *       1 :SHL: 5
IOMD_VIDCR_Dup          *       1 :SHL: 7

; Bits in DRAMCR

IOMD_DRAMCR_DRAM_Large  *       4_00    ; 1M, 4M, 16M DRAM
IOMD_DRAMCR_DRAM_Small  *       4_01    ; 256K DRAM

 [ MorrisSupport
IOMD_Original           *       &D4E7
IOMD_7500               *       &5B98
IOMD_7500FE             *       &AA7C
 ]

; Registers not strictly in IOMD, but in IOMD-based systems

IOMD_MonitorType        *       &03310000
IOMD_MonitorIDMask      *       &01     ; only bottom bit valid
; Mouse buttons are in bits 4..6
IOMD_ProtectionLinkBit  *       &80     ; zero => protected against delete power-on etc
IOMD_SoundsystemLinkBit  *      &100    ; zero => Rimmer, so assume 16bit sound DAC's

; Bases for new 'extended address space' expansion cards

IOMD_EASI_Base0         *       &08000000
IOMD_EASI_Base1         *       &09000000
IOMD_EASI_Base2         *       &0A000000
IOMD_EASI_Base3         *       &0B000000
IOMD_EASI_Base4         *       &0C000000
IOMD_EASI_Base5         *       &0D000000
IOMD_EASI_Base6         *       &0E000000
IOMD_EASI_Base7         *       &0F000000

 ]

        END
