; Copyright 1996 Acorn Computers Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
;     http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
; > hdr:ARM600

; ********************
; *** Changes List ***
; ********************

; 13-Jan-93 TMD Created.
; 12-Mar-93 TMD Added SetCop, ReadCop and CR_foo symbols
; 10-Aug-93 SMC Added condition fields to SetCop and ReadCop

VIDC            EQU     &03500000

; Access privilege bits

AP_ROM  *       4_0             ; user read-only,  svc read-only   (if R bit set in CR)
AP_None *       4_1             ; user no access,  svc read/write
AP_Read *       4_2             ; user read-only,  svc read/write
AP_Full *       4_3             ; user read/write, svc read/write

L1_AP     *     4_300000        ; masks for AP fields
L2_AP     *     4_333300
L2X_AP    *     4_000300

L1_APMult *     4_100000        ; value to multiply AP_ values by for L1 entry
L2_APMult *     4_111100        ; value to multiply AP_ values by for L2 entry with same AP for each sub-page
L2T_APMult *    4_000100        ; value to multiply AP_ values by for tiny or extended L2 entry
L2X_APMult *    L2T_APMult

L1_DomainShift *   5            ; lowest bit position in L1 entry for domain number

L1_Fault *      4_0             ; translation fault specifier in L1 entry
L1_Page *       4_1             ; coarse page specifier in L1 entry
L1_Section *    4_2             ; section (or supersection) specifier in L1 entry
L1_Fine *       4_3             ; fine page specifier in L2 entry

L2_Fault *      4_0             ; translation fault specifier in L2 entry
L2_LargePage *  4_1             ; large page specifier in L2 entry
L2_SmallPage *  4_2             ; small page specifier in L2 entry
L2_TinyPage  *  4_3             ; tiny page specifier in L2 entry (fine only)
L2_ExtPage *    4_3             ; extended page specifier in L2 entry (XScale - coarse only)

L1_TEXShift *   12
L1_TEX  *       2_1111 :SHL: 12 ; Type Extension bits
L1_X    *       1 :SHL: 12      ; XScale - modifies meaning of C and B bits
L1_P    *       1 :SHL: 9       ; page bit in level 1 entry (XScale - ECC enable on 80200)
L1_U    *       1 :SHL: 4       ; updateable bit in level 1 entry (ARM6 only, not ARM7+)
L1_C    *       1 :SHL: 3       ; cacheable  --------""----------
L1_B    *       1 :SHL: 2       ; bufferable --------""----------
L1_SS   *       1 :SHL: 18      ; supersection
L1_SSb36Shift * 5               ; physical address 39:36 in supersections
L1_SSb36Width * 4
L1_SSb36Mask *  1:SHL:(L1_SSb36Shift+L1_SSb36Width) - 1:SHL:L1_SSb36Shift
L1_SSb32Shift * 20              ; physical address 35:32 in supersections
L1_SSb32Width * 4
L1_SSb32Mask *  1:SHL:(L1_SSb32Shift+L1_SSb32Width) - 1:SHL:L1_SSb32Shift

L2L_TEXShift *  12
L2_TEXShift *   6
L2L_TEX *       2_1111 :SHL: 12 ; Type Extension bits (large pages)
L2_TEX  *       2_1111 :SHL: 6  ; Type Extension bits (tiny and extended pages)
L2L_X   *       1 :SHL: 12      ; XScale - modifies meaning of C and B bits (large pages)
L2_X    *       1 :SHL: 6       ; XScale - modifies meaning of C and B bits (tiny and extended pages)
L2_C    *       1 :SHL: 3       ; cacheable  bit in level 2 entry
L2_B    *       1 :SHL: 2       ; bufferable --------""----------

; MMU control register bits

MMUC_M  *       1 :SHL: 0       ; MMU enable
MMUC_A  *       1 :SHL: 1       ; Address fault enable
MMUC_C  *       1 :SHL: 2       ; Cache enable (or Data cache enable)
MMUC_W  *       1 :SHL: 3       ; Write buffer enable
MMUC_P  *       1 :SHL: 4       ; 32-bit program space enable
MMUC_D  *       1 :SHL: 5       ; 32-bit data space enable
MMUC_L  *       1 :SHL: 6       ; Late abort mode enable
MMUC_B  *       1 :SHL: 7       ; Big-endian mode enable
MMUC_S  *       1 :SHL: 8       ; S-mode enable
MMUC_R  *       1 :SHL: 9       ; R-mode enable (ARM7 or later)
MMUC_F  *       1 :SHL: 10      ; Coprocessor frequency bit (ARM700 only)
MMUC_Z  *       1 :SHL: 11      ; Branch predictor enable
MMUC_I  *       1 :SHL: 12      ; Instruction cache enable
MMUC_V  *       1 :SHL: 13      ; High exception vectors
MMUC_RR *       1 :SHL: 14      ; Round-robin replacement
MMUC_L4 *       1 :SHL: 15      ; Disable ARMv5 "load Thumb state with PC" behaviour
MMUC_nF *       1 :SHL: 30      ; not FastBus (ie separate CPUCLK from MEMCLK)
MMUC_iA *       1 :SHL: 31      ; Asynchronous

; ARM600 MMU coprocessor number

Arm600Cop CP      15

; ARM600 coprocessor registers

CR_Dummy        CN      0
CR_ID           CN      0       ; read-only
CR_Control      CN      1       ; write-only
CR_TTabBase     CN      2       ; write-only
CR_Domains      CN      3       ; write-only
CR_FaultStatus  CN      5       ; read
CR_TLBFlush     CN      5       ; write
CR_FaultAddress CN      6       ; read
CR_TLBPurge     CN      6       ; write
CR_IDCFlush     CN      7       ; write-only

; Cache type register fields
; NOTE - need to be kept in sync with hdr.MEMM.VMSAv6!

CT_ctype_pos    *       25
CT_ctype_mask   *       &F:SHL:CT_ctype_pos
CT_S_pos        *       24
CT_S            *       1:SHL:CT_S_pos
CT_Dsize_pos    *       12
CT_Dsize_mask   *       &FFF:SHL:CT_Dsize_pos
CT_Isize_pos    *       0
CT_Isize_mask   *       &FFF:SHL:CT_Isize_pos

CT_ctype_WT     *       0       ; write-through cache
CT_ctype_WB_Crd *       1       ; write-back, clean by reading data
CT_ctype_WB_CR7 *       2       ; write-back, clean with register 7
CT_ctype_WB_Cal_LD  *   5       ; write-back, clean by allocating data, lockdown (?)
CT_ctype_WB_CR7_LDd *   5       ; write-back, clean with register 7, lockdown (format D)
CT_ctype_WB_CR7_LDa *   6       ; write-back, clean with register 7, lockdown (format A)
CT_ctype_WB_CR7_LDb *   7       ; write-back, clean with register 7, lockdown (format B)
CT_ctype_WB_CR7_Lx  *   8       ; write-back, clean with register 7, multiple cache levels
CT_ctype_WB_CR7_LDc *  14       ; write-back, clean with register 7, lockdown (format C)

CT_P_pos        *       11
CT_P            *       1:SHL:CT_P_pos
CT_size_pos     *       6
CT_size_mask    *       7:SHL:CT_size_pos
CT_assoc_pos    *       3
CT_assoc_mask   *       7:SHL:CT_assoc_pos
CT_M_pos        *       2
CT_M            *       1:SHL:CT_M_pos
CT_len_pos      *       0
CT_len_mask     *       3:SHL:CT_len_pos

CT_size_512     *       0
CT_size_1K      *       1
CT_size_2K      *       2
CT_size_4K      *       3
CT_size_8K      *       4
CT_size_16K     *       5
CT_size_32K     *       6
CT_size_64K     *       7
CT_size_128K    *       8
CT_size_768     *       0
CT_size_1536    *       1
CT_size_3K      *       2
CT_size_6K      *       3
CT_size_12K     *       4
CT_size_24K     *       5
CT_size_48K     *       6
CT_size_96K     *       7
CT_size_192K    *       8

CT_assoc_1      *       0
CT_assoc_2      *       1
CT_assoc_4      *       2
CT_assoc_8      *       3
CT_assoc_16     *       4
CT_assoc_32     *       5
CT_assoc_64     *       6
CT_assoc_128    *       7
CT_assoc_0      *       0
CT_assoc_3      *       1
CT_assoc_6      *       2
CT_assoc_12     *       3
CT_assoc_24     *       4
CT_assoc_48     *       5
CT_assoc_96     *       6
CT_assoc_192    *       7

CT_len_2        *       0
CT_len_4        *       1
CT_len_8        *       2
CT_len_16       *       3

CT_M_512        *       0
CT_M_1K         *       0
CT_M_2K         *       0
CT_M_4K         *       0
CT_M_8K         *       0
CT_M_16K        *       0
CT_M_32K        *       0
CT_M_64K        *       0
CT_M_128K       *       0
CT_M_768        *       1
CT_M_1536       *       1
CT_M_3K         *       1
CT_M_6K         *       1
CT_M_12K        *       1
CT_M_24K        *       1
CT_M_48K        *       1
CT_M_96K        *       1
CT_M_192K       *       1



        MACRO
        SetCop  $reg, $cop, $cc
        MCR$cc  Arm600Cop, 0, $reg, $cop, CR_Dummy
        MEND

        MACRO
        ReadCop $reg, $cop, $cc
        MRC$cc  Arm600Cop, 0, $reg, $cop, CR_Dummy
        MEND


        END
