
;
; >ATAFS::DataBase.$.Apps.MyApps.SID.Demos.Binary.Warnings
;
; Disassembled by SID on Wed,30 Oct 2002.02:39:46
;

        GET     Hdr:ListOpts
        GET     Hdr:Macros
        GET     Hdr:System
        GET     Hdr:Services


        AREA    |Asm$$Code|, CODE, READONLY


; ******************************************************************************
;
; <- Main entry point
;
Module_BaseAddr                                         ; Address &0, referenced once
        BEQ     skip
        MSR     CPSR_f,#&80000000
        MSR     CPSR_c,#&0F                             ; Warning: Immediate form of MSR is unpredictable for fields other than flags
        MSR     SPSR_f,#&D0000000
        MSR     CPSR_c,R5
        MSR     SPSR_c,R5
        MSREQ   CPSR_c,R5                               ; Warning: StrongARM bug: following instruction is executed twice
        MSREQ   SPSR_c,R5
        MSREQ   CPSR_f,#&F0000000
        MSREQ   CPSR_c,#&0F                             ; Warning: Immediate form of MSR is unpredictable for fields other than flags
        MSREQ   SPSR_f,#&20000000
        MSREQ   SPSR_c,#7                               ; Warning: Immediate form of MSR is unpredictable for fields other than flags
        LDMIA   R13!,{R0-R3,PC}^                        ; Warning: May be unsafe in 32-bit modes
skip                                                    ; Address &34, referenced once
        MOVVC   PC,R14
        STMDB   R13!,{R0-R3,R14}^                       ; *** ! and ^
        TEQP    R0,#3                                   ; Warning: May be unsafe in 32-bit modes
        MOVEQS  PC,R14                                  ; Warning: May be unsafe in 32-bit modes
        LDMEQIA R0,{R1-R9}                              ; Warning: Conditional LDM/STM slow on StrongARM and XScale
        STMEQIA R0,{R1,R9}                              ; Warning: Conditional LDM/STM slow on StrongARM and XScale
        LDR     R0,[R1],#0                              ; Warning: Use the LDR Rd,[Rn,#0] form in preference
        STR     R0,[R1],#0                              ; Warning: Use the STR Rd,[Rn,#0] form in preference
        DCI     &E8900000                               ; Warning: Undefined or unpredictable instruction
        DCI     &E8800000                               ; Warning: Undefined or unpredictable instruction
        DCI     &E8B00000                               ; Warning: Undefined or unpredictable instruction
        DCI     &E8A00000                               ; Warning: Undefined or unpredictable instruction
        Push    "R0,R14"
        Pull    "R0,PC", EQ                             ; Warning: Conditional LDM/STM slow on StrongARM and XScale
        BIC     R0,R14,#&F0000000
        BIC     R0,R14,#&FC000000                       ; Warning: May be unsafe in 32-bit modes
        BIC     R0,R14,#&FC000003                       ; Warning: May be unsafe in 32-bit modes
        ORR     R0,R14,#&F0000003                       ; Warning: May be unsafe in 32-bit modes
        SWILS   XOS_Byte
        MOVLS   R0,R1
        MOVHI   PC,R14
        MOVLS   PC,R11
data_1                                                  ; Address &8C, not referenced
        DCD     &E1A00000
        DCD     0
        DCD     0
        DCB     "ޭޭޭHello. I am a string.", 0
        ALIGN
data                                                    ; Address &B8, not referenced

        END

