


		===============================
		SILOS III Demonstration Version
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SPECIAL NOTICE  -       The SILOS III Demonstration Program is
			designed to be used for demonstration
			purposes only.  The program has specific
			limitations to prevent usage for commercial
			purposes.  There are features and capabilities
			which are intentionally reduced or disabled.

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SYSTEM REQUIREMENTS: 

1)      386, 486 PC compatible computer.

2)      4 MB of memory minimum, 8 MB recommended. 

3)      4 MB available disk space required to install SILOS III.
	Note:  The disk space required during simulation depends 
	       on the circuit size and simulation activity.

4)      Windows 3.1 or higher.

5)      DOS 3.3 or higher.


FILE LIST:

The files in the SILOS III program have been compressed and can
only be installed by running the setup program on the SILOS III
Diskette.


SILOS3W.EXE     -       SILOS III program.

SILOS3W.HLP             SILOS III help file.

SDA.EXE         -       Silos Data Analyzer program.

SDA.HLP         -       Silos Data Analyzer help file.

README.TXT      -       This file.


EXAMPLES SUBDIRECTORY

ANALOG.V      -         Analog to Digital converter circuit that
			models the analog portion at the behavioral
			level and the digital portion at the 
			gate level.  To run this example use the 
			"File/New/Input" menu selection to open the 
			"Input File" dialog box and then input file 
			"ANALOG.V".  To simulate the circuit use the 
			"LogicSim/Run logic simulation" menu 
			selection to open the "Simulate" dialog box
			and press the "Simulate" button.  To view the
			results use the "Analyzer/Start" analyzer
			menu selection to open the Silos Data Analyzer
			and then use the "Select/Display list" menu
			selection to open the "Select Display List"
			dialog box.  Use the "Clear" button to clear
			any previously displayed signals and then select
			the Display Group "analog" and press the 
			"Ok" button.  

EXAM1.V        -        Tutorial Example   
			4-bit shift register using switch and gate 
			level primitives. To run this example use the 
			"File/New/Input" menu selection to open the 
			"Input File" dialog box and then input file 
			"EXAM1.V".  To simulate the circuit use the 
			"LogicSim/Run logic simulation" menu 
			selection to open the "Simulate" dialog box
			and press the "Simulate" button.  To view the
			results use the "Analyzer/Start" analyzer
			menu selection to open the Silos Data Analyzer
			and then use the "Select/Display list" menu
			selection to open the "Select Display List"
			dialog box.  Use the "Clear" button to clear
			any previously displayed signals and then select
			the Display Group "exam1" and press the 
			"Ok" button.  

EXAM2.V      -          Tutorial Example   
			Fault simulation example.
			This circuit is a 4-bit shift register at 
			the switch and gate level.  To run this example 
			input "EXAM2.V" and run fault simulation to 
			time=1000 using a strobe of 50.  Then use the 
			faults report to view the results.
			See the Tutorial for more information.

RISC_CPU.V      -       RISC microprocessor example demonstrating 
			standard Verilog HDL code.  To run this 
			example use the "File/New/Input" menu 
			selection to open the "Input File" dialog 
			box and then input file "RISC_CPU.V".  
			To simulate the circuit use the 
			"LogicSim/Run logic simulation" menu 
			selection to open the "Simulate" dialog box
			and press the "Simulate" button.  To view the
			results use the "Analyzer/Start" analyzer
			menu selection to open the Silos Data Analyzer
			and then use the "Select/Display list" menu
			selection to open the "Select Display List"
			dialog box.  Use the "Clear" button to clear
			any previously displayed signals and then select
			the Display Group "risc_cpu" and press the 
			"Ok" button.  

SAVE.GRP	-	This file contains the "Display List" 
			signal groups for viewing the circuits 
			"analog.v", "exam1.v","exam2.v", 
			"risc_cpu.v" and "traffic.v" with the 
			Silos Data Analyzer.  

TRAFFIC.V      -        Traffic light controller example from 
			OVI Verilog Language Reference Manual.  
			This circuit demonstrates standard 
			Verilog HDL code.  To run this example use the 
			"File/New/Input" menu selection to open the 
			"Input File" dialog box and then input file 
			"TRAFFIC.V".  To simulate the circuit use the 
			"LogicSim/Run logic simulation" menu 
			selection to open the "Simulate" dialog box
			and press the "Simulate" button.  To view the
			results use the "Analyzer/Start" analyzer
			menu selection to open the Silos Data Analyzer
			and then use the "Select/Display list" menu
			selection to open the "Select Display List"
			dialog box.  Use the "Clear" button to clear
			any previously displayed signals and then select
			the Display Group "traffic" and press the 
			"Ok" button.  


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IMPORTANT NOTICE
****************


All versions of SILOS III, including this limited demonstration license, 
shall be treated as the confidential property of SIMUCAD, Inc.

This limited demonstration license is granted by SIMUCAD, Inc. and is
subject to the following conditions and limitations:

1)      There are no restrictions on making copies of this demonstration
	version of SILOS III (software and documentation).

2)      No person will decompile or disassemble this program or by any
	other similar means of reverse engineering undertake to discover
	the ideas, information and algorithms embodied in this program.

3)      This license is granted solely for the purpose of evaluating 
	SILOS III and use of this license for commercial purposes is
	strictly forbidden.



				WARRANTY

SIMUCAD makes no warranty of any kind, express or implied including,
without limitation, any warranties of merchantability and/or fitness
for a particular purpose. Simucad shall not be liable for any damages, 
whether direct, indirect, special or consequential arising from a
failure of the program to operate in the manner desired by the user.
Simucad shall not be liable for any damage to any property that may
be caused directly or indirectly by the software or duplication of
the software.


IN NO EVENT WILL SIMUCAD BE LIABLE FOR ANY DAMAGES INCLUDING ANY
LOST PROFITS, LOST SAVINGS OR OTHER INCIDENTAL OR CONSEQUENTIAL
DAMAGES ARISING OUT OF INABILITY TO USE THE PROGRAM, OR FOR ANY
OTHER CLAIM BY ANY OTHER PARTY.

