Patch-ID# 103346-06
Keywords: Ultra Enterprise flashprom update
Synopsis: SunOS 5.5.1: Ultra Enterprise 3000/4000/5000/6000 flashprom update
Date: Jul/22/97

Solaris Release: 2.5.1

SunOS Release: 5.5.1

Unbundled Product: 

Unbundled Release: 

Relevant Architectures: sun4u Ultra Enterprise 3000/4000/5000/6000 only

BugId's fixed with this patch: 1245745

Changes incorporated in this version: 

Patches accumulated and obsoleted by this patch: 

Patches which conflict with this patch: 

Patches required with this patch: 

Obsoleted by: 

Files included with this patch: 

Problem Description: 

1245745: Create unix version of flash-update for UltraEnterprise Servers Prom's


Patch Installation Instructions: 
-------------------------------- 

Special Install Instructions: 
----------------------------- 

	NOTE:	Please read this entire file before proceeding to update
		the flash proms on your system.


The above mentioned series of machines contain their firmware in flashproms
that can be programmed with new code while the machine is up and running
unix. The reprogrammed flashproms take affect next time you reset the machine.


Here are the recommended steps to download the latest firmware on your system:

    1)  Login as root on the system whose firmware needs to be
	upgraded.

    2)  Execute the binary './flash-update' in this directory.

		a) It first extracts the flashprom driver from itself
		   and installs the driver on the system.

		b) Next it extracts the program that actually flash
		   updates the proms with the right images.

    3)  The program display the current revision of the proms in
	your system. It then displays the versions that are available
	in the release of the flash-update-<n> program that you have
	executed.

    3)  The program will display its progress at every step. Here
	is a sample output where a machine has boards 0, 1, 4, 5
	and 6 and its flash proms are being updated:


# ./flash-update-<latest-rev>
Generating flashprom driver...
Generating SUNW,Ultra-Enterprise flash-update program...

Current System Board PROM Revisions:
------------------------------------
Board  0:        cpu OBP   3.2.2 1996/03/20 10:07 POST  3.0.3 1996/03/16 17:54
Board  4:        cpu OBP   3.2.2 1996/03/20 10:07 POST  3.0.3 1996/03/16 17:54
Board  1:  dual-sbus FCODE 1.7.0 1996/03/20 10:07 iPOST 3.0.3 1996/03/16 17:55
Board  5:   upa-sbus FCODE 1.7.0 1996/03/20 10:07 iPOST 3.0.3 1996/03/16 17:55
Board  6:  dual-sbus FCODE 1.7.0 1996/03/20 10:07 iPOST 3.0.3 1996/03/16 17:55


Available 'Update' Revisions:
-----------------------------

                 cpu OBP   3.2.3 1996/04/04 20:23 POST  3.1.4 1996/04/04 20:23
           dual-sbus FCODE 1.7.0 1996/04/04 20:23 iPOST 3.1.4 1996/04/04 20:23
            upa-sbus FCODE 1.7.0 1996/04/04 20:23 iPOST 3.1.4 1996/04/04 20:23

Verifying Checksums: Okay


Do you wish to flash update your firmware? y/[n] : y	<----- Enter y here

Are you sure? y/[n] : y					<----- Enter y here


Updating Board 0: Type 'cpu'
1 Erasing ... Done.
1 Verifying Erase ... Done.
1 Programming ... Done.
1 Verifying Program ... Done.

Updating Board 4: Type 'cpu'
1 Erasing ... Done.
1 Verifying Erase ... Done.
1 Programming ... Done.
1 Verifying Program ... Done.

Updating Board 1: Type 'dual-sbus'
1 Erasing ... Done.
1 Verifying Erase ... Done.
1 Programming ... Done.
1 Verifying Program ... Done.

Updating Board 5: Type 'upa-sbus'
1 Erasing ... Done.
1 Verifying Erase ... Done.
1 Programming ... Done.
1 Verifying Program ... Done.

Updating Board 6: Type 'dual-sbus'
1 Erasing ... Done.
1 Verifying Erase ... Done.
1 Programming ... Done.
1 Verifying Program ... Done.
#


	NOTE:	The flash proms are write protected by either of the
		following two conditions:
		
			a) Front panel key switch in secure mode.
			b) Jumper (P601) removed on clock board.

		At the time of writing this document systems are
		shipped with the jumper on the clock board installed.
		This means that only the front panel key switch
		being in secure position write protects the proms.

		If the proms are detected to be write protected then
		the flash update process will fail with the following
		message:

FPROM Write Protected: Check Write Enable Jumper or Front Panel Key Switch.


		If there is a power failure while the flash proms are
		being upgraded then you need to follow steps listed
		in the document:

			Ultra Enterprise 6000/5000/4000/3000
			System Flash PROM Programming Guide
			Part No.: 802-5579-10
			Rev. A, March 1996


	The data under the "Current System Board PROM Revisions:"
	label lists:

		a) Board number
		b) Board type:
			1) cpu:		CPU/Memory
			2) dual-sbus:	IO Type 1
			3) upa-sbus:	IO Type 2
		c) OpenBoot/FCODE revision
		d) OpenBoot/FCODE date and time
		e) POST/iPOST revision
		f) POST/iPOST date and time


	The data under the "Available 'Update' Revisions:" lists the
	following (for each type of board). These are the images that
	are going to be installed on your boards if you answer 'y' to
	the two questions:

		a) Type of image
		b) OpenBoot/FCODE revision
		c) Openboot/FCODE date/time
		d) POST/iPOST revision
		e) POST/iPOST date and time

	
	Once you answer yes to the two questions the flash update
	of the proms images starts. Any other response gets you out
	of the flash-update process.

	Information is displayed for each board being updated.

	There are four parts to the update process:

		1) Erasing the flash prom.
		2) Verifying that the erase actually happened.
		3) Programming flash proms with the new images.
		4) Verifying that the programming was without errors.

	The number displayed on the left most column is the pass number.
	If either of the 4 steps listed above fail then all the 4 steps
	have to be repeated and the pass number is incremented.


    4)  Once the flash update program completes it removes the flashprom
	driver from the machine. It also cleans up the temporary files
	that it created in the /tmp directory.

    5)  Next time when you halt and reboot your system please
	power-cycle the system for the new flashproms to take
	affect.


Since this directory will contain all revisions of the firmware
released for these machine you can follow the same steps to downrev
your firmware if the need ever arises. Execute the correct revision
of the flash-upate-<n> program. The higher revision number of this
patch will contain a newer release of the firmware.




Version -01 specific information:
---------------------------------

The version -01 of flash-update in this directory contains the following rev
of the firmware:

	CPU/Memory Board:
		 Ultra Enterprise 3.2 Version 3 created 1996/04/04 20:23
		 POST 3.1.4 1996/04/04 20:23

	IO Graphics Board:
		 I/O Type 2 1996/04/04 20:23 
		 iPOST 3.1.4 1996/04/04 20:23

	Dual Sbus IO Board:
		 I/O Type 1 1996/04/04 20:23 
		 iPOST 3.1.4 1996/04/04 20:23




Version -02 specific information:
---------------------------------


	CPU/Memory Board:
		 Ultra Enterprise 3.2 Version 4 created 1996/05/30 11:17
		 POST 3.2.2 1996/05/29 19:46

	IO Graphics Board:
		 I/O Type 2 1996/05/30 11:17 
		 iPOST 3.2.2 1996/05/29 19:46

	Dual Sbus IO Board:
		 I/O Type 1 1996/05/30 11:17 
		 iPOST 3.2.2 1996/05/29 19:46



Bugs fixed in this release for the firmware:

1246116 OBP prints incorrect about of memory in its banner
1244993 Unable to boot SunFire from NPI FDDI card 3.0/4.0
1248141 OBP needs to inform failed SIMM information to system
1250943 .speed command missing in Sunfire OBP
1246458 OBP prints incorrect ratio frequency in 2/3 mode
1254307 TODC checksum destroyed on power cycle




Version -03 specific information:
---------------------------------

	
	CPU/Memory Board:
		 Ultra Enterprise 3.2 Version 5 created 1996/06/24 14:55
		 POST 3.2.3 1996/06/24 16:03

	IO Graphics Board:
		 I/O Type 2 1996/05/30 11:17 
		 iPOST 3.2.2 1996/05/29 19:46

	Dual Sbus IO Board:
		 I/O Type 1 1996/05/30 11:17 
		 iPOST 3.2.2 1996/05/29 19:46


Bugs fixed in this release for the firmware:

4026135 Fatal Reset IPREP during POST


Version -04 specific information:
---------------------------------

	CPU/Memory Board:
		 Ultra Enterprise 3.2 Version 6 created 1996/10/14 18:01
		 POST 3.4.1 1996/10/15 17:08

	IO Graphics Board:
		 I/O Type 2 1996/05/30 11:17 
		 iPOST 3.4.1 1996/10/15 17:09

	Dual Sbus IO Board:
		 I/O Type 1 1996/05/30 11:17 
		 iPOST 3.4.1 1996/10/15 17:09



Bugs fixed in this release for the firmware:

1254337 System does not auto boot if component failures are discovered in POST
4006129 Fatal Reset MTIMEOUT when POST enters OBP
4006109 Some CPUs fail to checkin after the clock reset
1260643 OBP not masking failed component (CPU mod) fails POST
1256038 sunfire remote console needs to maintain continuous coverage

1256295 FFB speed sort boards not supported


Other changes/New Features/Enhancements:

 - Remove "help <name>" support in OBP because OBP runs out of ROM space.
 - To support new clock board and Ultrasparc II Modules in OBP.
	* Internal change in the user interface command set-sys-clk
	* Correct values of clock-frequency properties
 - Changes to POST frequency functions to support future (faster) Ultrasparc
   II Modules (NOTE: Ultrasparc I Modules will now be set to run at 168MHz.)
 - POST will attempt deconfigure CPU modules that are not compatiable
   with the master CPU.
 - Support for larger SIMM (256MB) sizes added.

 - POST will now test a wider variety of frame-buffers.
 - POST will checksum the FCODE proms on plug-in cards,
   and report the device bad when a checksum fails.

Version -05 specific information:
---------------------------------

	CPU/Memory Board:
		 Ultra Enterprise 3.2 Version 7 created 1997/02/04 13:27
		 POST 3.5.1 1997/01/30 15:29

	IO Graphics Board:
		 I/O Type 2 FCODE 1.8.1 1996/12/12 18:22 
		 iPOST 3.4.2 1997/01/10 13:34

	Dual Sbus IO Board:
		 I/O Type 1 FCODE 1.8.1 1996/12/12 18:22 
		 iPOST 3.4.2 1997/01/10 13:34


Bugs fixed in this release for the firmware:

1260863 2 2 XIR can cause a fatal error
1260643 E6000 OBP not masking failed component (CPU mod) fails POST


Other changes/New Features/Enhancements:

 - Use SUNW,UltraSPARC-II instead of SUNW,UltraSPARC for BlackBird cpu-node
   name.
 - Support 4MB-ecache BlackBird modules, CPU eache-size property contains
   appropriate value to stand for usable ecache size.
 - Increase user space from 32KB to 96KB in order to support big IO
   configuration  (It can support maximum 15 IO boards with fully plugged-in
   SBus or PCI cards.)
 - Support new PCI boards.
 - Support new SOC+ IO/IOG boards.
 - Support CPU hot-plug but disable OS interface words SUNW,shutdow-self
   and SUNW,wakeup-cpu.

 - Rmote XIR and Button XIR operation hang problem fixed.
   (fixed the multiple XIR master bug and changed the 
   soft reset after the XIR to use the clock board reset
   to make it synchonous)
 - Includes support to configure new IO boards
	   (with the SOC+ installed). 
 - Includes support to configure larger Ecache modules.

The general rules for mixing CPU modules with various ecache
sizes as supported with this CPU PROM release.

NOTES:
1. Don't mix UltraSparcI Modules with UltraSparcII Modules.
2. old CPU System Boards  can support up to a 2Mbyte Ecache Module
3. new CPU System Boards can support up to an 8Mbyte Ecache Module
4. OBP and prtdiag only report the configured ecache size, not the actual size
   POST always reports the actual cache size present.

UltraSparc I

	The general rule: 
	Various ecache sizes, up to the maximum supported by the system
	board in use (2MB or 4MB), are supported in the system as long
	as both Modules on the system board have the same size ecache.

	NOTE: A 4MB UltraSparcI (if ever) requires the newer System Board.

	If both modules on the system board have the same size
	ecache, then configure for the size of ecache.

	If modules on the system board have different size
	ecache, then deconfigure the slave CPU module on that
	system board (usually the odd numbered module).

UltraSparc II

	The general rule:
	Various ecache sizes, up to the maximum supported by the system
	board in use (2MB or 4MB), are supported in the system.

	NOTE: When a 4MB Modules is installed on older System Boards
	it will be configured for a cache size of 2MB.

	If both modules on the system board have the same size
	ecache, then configure for the size of ecache.	

	If modules on the system board have different size
	ecache, then configure the size of the cache to be the
	smaller of the 2 modules ecache.

Version -06 specific information:
---------------------------------

	CPU/Memory Board:
		 Ultra Enterprise 3.2 Version 8 created 1997/04/10 16:26
		 POST 3.6.1 1997/04/17 13:37

	IO Graphics Board:
		 I/O Type 2 FCODE 1.8.1 1996/12/12 18:22 
		 iPOST 3.4.2 1997/01/10 13:34

	Dual Sbus IO Board:
		 I/O Type 1 FCODE 1.8.1 1996/12/12 18:22 
		 iPOST 3.4.2 1997/01/10 13:34

	Dual PCI IO Board:
		 I/O Type 3 FCODE 1.8.7 1997/05/09 11:18 
		 iPOST 3.0.2 1997/05/01 10:56

Bugs fixed in this release for the firmware:

Other changes/New Features/Enhancements:
. Added functionality to support processor power control for Solaris 2.6.
. Added the PCI I/O error handler to take care of Psycho, Pci_bus, onboard
  Cheerio, onboard Isp1040 errors passed by new POST.
. Created the appropriate dummy sbus node for the broken SYSIO chip instead
  of probing the FCode on the IO board to create the sbus node.
  This fixes the Fatal Reset problem caused by probing the broken SYSIO.
. Improved .xir-state-all to print valid xir states.
. Resync'ed catchexc.fth with Desktop OBP to restore Forth stacks in (crestart)
  which is claimed to fix for L1-A bugs 1223421, 1229983, 1244597. But I
  still saw the L1-A bug 1229983 exists, though the change is necessary.
. Updated POST error reporting mechanism to handle pci board component failures.

NOTE: This is the first release version to support PCI IO boards officially.
  User should upgrade the system firmware with no PCI IO boards plugged in.