Patch-ID# 103346-10 Keywords: Ultra Enterprise UNIX flashprom update 3.2.12 Synopsis: Hardware/PROM: Ultra Enterprise 3x00/4x00/5x00/6x00 UNIX flashprom update Date: Feb/03/98 Solaris Release: 2.5.1 & 2.6 & 2.7 SunOS Release: 5.5.1 & 5.6 & 5.7 Unbundled Product: Hardware/PROM Unbundled Release: CPU: OBP 3.2.12; IO Type 1/2: 1.8.3; IO Type 3: 1.8.7; IO Type 4/5: 1.8.7 NOTE: This utility is *not* Solaris Release version dependent. The list of releases shown under the "Solaris Release" and "SunOS Release" sections may not be complete. Flash-update-10 or later version can run on any 32bit or 64bit OS. Flash-update-09 or earlier version may run on any 32bit OS, but not on any 64bit OS. Relevant Architectures: sun4u Ultra Enterprise 3000/4000/5000/6000 only BugId's fixed with this patch: 1245745 1246116 1244993 1248141 1250943 1246458 1254307 4026135 1254337 4006129 4006109 1260643 1256038 1256295 1260863 1260643 4055485 4056652 4058035 4071558 4073702 4045138 4092765 4086435 4018294 4041025 4024106 4078557 4088491 4102394 4102353 Changes incorporated in this version: 4041025 4024106 4078557 4088491 4102394 4102353 Patches accumulated and obsoleted by this patch: Patches which conflict with this patch: Patches required with this patch: Obsoleted by: Files included with this patch: Problem Description: 1245745: Create unix version of flash-update for UltraEnterprise Servers Prom's It upgrades to CPU prom version 3.2.11, IO/IOG proms version 1.8.3, and SOC+ IO/IOG proms version 1.8.7. (From 103346-10) 4041025 (2/2): single-stepping over some sethi instructions is broken 4024106 (2/1): kadb :c often causes panics 4078557 (3/3): sunfire devalias net,cdrom,disk not correct for PCI board 4088491 (2/3): Console escape sequence panics sun4u systems 4102394 (4/4): RFE to add default devaliases for FCAL internal drive for Duraflame+ system. 4102353 (3/2): hot-plug cpu/memory board, fatal reset at reboot, sunfire system Please see the section "Version -10 specific information" for other changes. (From 103346-09) 4045138 (2/3): POST fails to detect faulty 167Mhz processor 4092765 (2/3): E3000..E6000 POST hangs during fcopy operation with new Am29F040B flashprom. 4086435 (2/2): UE6000 with latest kernel/OBP patches, fails to drop to kadb. 4018294 (1/1): client-tte-handler not called for large addresses. Please see the section "Version -09 specific information" for other changes. (From 103346-08) 4071558 (1/5): Fatal Error Reset message displays wrong year (Year 2000 compliant issue) 4073702 (2/2): E5000 hanging with messages: Fatal error Please see the section "Version -08 specific information" for other changes. (From 103346-07) 4055485 (1/1): FFB2 fails OBP 4056652 (1/1): SunFire proms have wrong parameters 4058035 (4/5): "CPU tick sync" console message when restarting a powered-off CPUPlease see the section "Version -07 specific information" for other changes. (From 103346-06) Please see the section "Version -06 specific information" for changes. (From 103346-05) 1260863 2 2 XIR can cause a fatal error 1260643 E6000 OBP not masking failed component (CPU mod) fails POST Please see the section "Version -05 specific information" for other changes. (From 103346-04) 1254337 System does not auto boot if component failures are discovered in POST 4006129 Fatal Reset MTIMEOUT when POST enters OBP 4006109 Some CPUs fail to checkin after the clock reset 1260643 OBP not masking failed component (CPU mod) fails POST 1256038 sunfire remote console needs to maintain continuous coverage 1256295 FFB speed sort boards not supported Please see the section "Version -04 specific information" for other changes. (From 103346-03) 4026135 Fatal Reset IPREP during POST (From 103346-02) 1246116 OBP prints incorrect about of memory in its banner 1244993 Unable to boot SunFire from NPI FDDI card 3.0/4.0 1248141 OBP needs to inform failed SIMM information to system 1250943 .speed command missing in Sunfire OBP 1246458 OBP prints incorrect ratio frequency in 2/3 mode 1254307 TODC checksum destroyed on power cycle Patch Installation Instructions: -------------------------------- Special Install Instructions: ----------------------------- NOTE: Please read this entire file before proceeding to update the flash proms on your system. The above mentioned series of machines contain their firmware in flashproms that can be programmed with new code while the machine is up and running unix. The reprogrammed flashproms take affect next time you reset the machine. Here are the recommended steps to download the latest firmware on your system: 1) Login as root on the system whose firmware needs to be upgraded. 2) Execute the binary './flash-update' in this directory. a) It first extracts the flashprom driver from itself and installs the driver on the system. b) Next it extracts the program that actually flash updates the proms with the right images. 3) The program display the current revision of the proms in your system. It then displays the versions that are available in the release of the flash-update- program that you have executed. 3) The program will display its progress at every step. Here is a sample output where a machine has boards 0, 1, 4, 5 and 6 and its flash proms are being updated: # ./flash-update- Generating flashprom driver... Generating SUNW,Ultra-Enterprise flash-update program... Current System Board PROM Revisions: ------------------------------------ Board 0: cpu OBP 3.2.2 1996/03/20 10:07 POST 3.0.3 1996/03/16 17:54 Board 4: cpu OBP 3.2.2 1996/03/20 10:07 POST 3.0.3 1996/03/16 17:54 Board 1: dual-sbus FCODE 1.7.0 1996/03/20 10:07 iPOST 3.0.3 1996/03/16 17:55 Board 5: upa-sbus FCODE 1.7.0 1996/03/20 10:07 iPOST 3.0.3 1996/03/16 17:55 Board 6: dual-sbus FCODE 1.7.0 1996/03/20 10:07 iPOST 3.0.3 1996/03/16 17:55 Available 'Update' Revisions: ----------------------------- cpu OBP 3.2.3 1996/04/04 20:23 POST 3.1.4 1996/04/04 20:23 dual-sbus FCODE 1.7.0 1996/04/04 20:23 iPOST 3.1.4 1996/04/04 20:23 upa-sbus FCODE 1.7.0 1996/04/04 20:23 iPOST 3.1.4 1996/04/04 20:23 Verifying Checksums: Okay Do you wish to flash update your firmware? y/[n] : y <----- Enter y here Are you sure? y/[n] : y <----- Enter y here Updating Board 0: Type 'cpu' 1 Erasing ... Done. 1 Verifying Erase ... Done. 1 Programming ... Done. 1 Verifying Program ... Done. Updating Board 4: Type 'cpu' 1 Erasing ... Done. 1 Verifying Erase ... Done. 1 Programming ... Done. 1 Verifying Program ... Done. Updating Board 1: Type 'dual-sbus' 1 Erasing ... Done. 1 Verifying Erase ... Done. 1 Programming ... Done. 1 Verifying Program ... Done. Updating Board 5: Type 'upa-sbus' 1 Erasing ... Done. 1 Verifying Erase ... Done. 1 Programming ... Done. 1 Verifying Program ... Done. Updating Board 6: Type 'dual-sbus' 1 Erasing ... Done. 1 Verifying Erase ... Done. 1 Programming ... Done. 1 Verifying Program ... Done. # NOTE: The flash proms are write protected by either of the following two conditions: a) Front panel key switch in secure mode. b) Jumper (P601) removed on clock board. At the time of writing this document systems are shipped with the jumper on the clock board installed. This means that only the front panel key switch being in secure position write protects the proms. If the proms are detected to be write protected then the flash update process will fail with the following message: FPROM Write Protected: Check Write Enable Jumper or Front Panel Key Switch. If there is a power failure while the flash proms are being upgraded then you need to follow steps listed in the document: Ultra Enterprise 6000/5000/4000/3000 System Flash PROM Programming Guide Part No.: 802-5579-10 Rev. A, March 1996 The data under the "Current System Board PROM Revisions:" label lists: a) Board number b) Board type: 1) cpu: CPU/Memory 2) dual-sbus: IO Type 1 3) upa-sbus: IO Type 2 c) OpenBoot/FCODE revision d) OpenBoot/FCODE date and time e) POST/iPOST revision f) POST/iPOST date and time The data under the "Available 'Update' Revisions:" lists the following (for each type of board). These are the images that are going to be installed on your boards if you answer 'y' to the two questions: a) Type of image b) OpenBoot/FCODE revision c) Openboot/FCODE date/time d) POST/iPOST revision e) POST/iPOST date and time Once you answer yes to the two questions the flash update of the proms images starts. Any other response gets you out of the flash-update process. Information is displayed for each board being updated. There are four parts to the update process: 1) Erasing the flash prom. 2) Verifying that the erase actually happened. 3) Programming flash proms with the new images. 4) Verifying that the programming was without errors. The number displayed on the left most column is the pass number. If either of the 4 steps listed above fail then all the 4 steps have to be repeated and the pass number is incremented. 4) Once the flash update program completes it removes the flashprom driver from the machine. It also cleans up the temporary files that it created in the /tmp directory. 5) Next time when you halt and reboot your system please power-cycle the system for the new flashproms to take affect. Since this directory will contain all revisions of the firmware released for these machine you can follow the same steps to downrev your firmware if the need ever arises. Execute the correct revision of the flash-upate- program. The higher revision number of this patch will contain a newer release of the firmware. Version -01 specific information: --------------------------------- The version -01 of flash-update in this directory contains the following rev of the firmware: CPU/Memory Board: Ultra Enterprise 3.2 Version 3 created 1996/04/04 20:23 POST 3.1.4 1996/04/04 20:23 IO Graphics Board: I/O Type 2 1996/04/04 20:23 iPOST 3.1.4 1996/04/04 20:23 Dual Sbus IO Board: I/O Type 1 1996/04/04 20:23 iPOST 3.1.4 1996/04/04 20:23 Version -02 specific information: --------------------------------- CPU/Memory Board: Ultra Enterprise 3.2 Version 4 created 1996/05/30 11:17 POST 3.2.2 1996/05/29 19:46 IO Graphics Board: I/O Type 2 1996/05/30 11:17 iPOST 3.2.2 1996/05/29 19:46 Dual Sbus IO Board: I/O Type 1 1996/05/30 11:17 iPOST 3.2.2 1996/05/29 19:46 Bugs fixed in this release for the firmware: 1246116 OBP prints incorrect about of memory in its banner 1244993 Unable to boot SunFire from NPI FDDI card 3.0/4.0 1248141 OBP needs to inform failed SIMM information to system 1250943 .speed command missing in Sunfire OBP 1246458 OBP prints incorrect ratio frequency in 2/3 mode 1254307 TODC checksum destroyed on power cycle Version -03 specific information: --------------------------------- CPU/Memory Board: Ultra Enterprise 3.2 Version 5 created 1996/06/24 14:55 POST 3.2.3 1996/06/24 16:03 IO Graphics Board: I/O Type 2 1996/05/30 11:17 iPOST 3.2.2 1996/05/29 19:46 Dual Sbus IO Board: I/O Type 1 1996/05/30 11:17 iPOST 3.2.2 1996/05/29 19:46 Bugs fixed in this release for the firmware: 4026135 Fatal Reset IPREP during POST Version -04 specific information: --------------------------------- CPU/Memory Board: Ultra Enterprise 3.2 Version 6 created 1996/10/14 18:01 POST 3.4.1 1996/10/15 17:08 IO Graphics Board: I/O Type 2 1996/05/30 11:17 iPOST 3.4.1 1996/10/15 17:09 Dual Sbus IO Board: I/O Type 1 1996/05/30 11:17 iPOST 3.4.1 1996/10/15 17:09 Bugs fixed in this release for the firmware: 1254337 System does not auto boot if component failures are discovered in POST 4006129 Fatal Reset MTIMEOUT when POST enters OBP 4006109 Some CPUs fail to checkin after the clock reset 1260643 OBP not masking failed component (CPU mod) fails POST 1256038 sunfire remote console needs to maintain continuous coverage 1256295 FFB speed sort boards not supported Other changes/New Features/Enhancements: - Remove "help " support in OBP because OBP runs out of ROM space. - To support new clock board and Ultrasparc II Modules in OBP. * Internal change in the user interface command set-sys-clk * Correct values of clock-frequency properties - Changes to POST frequency functions to support future (faster) Ultrasparc II Modules (NOTE: Ultrasparc I Modules will now be set to run at 168MHz.) - POST will attempt deconfigure CPU modules that are not compatiable with the master CPU. - Support for larger SIMM (256MB) sizes added. - POST will now test a wider variety of frame-buffers. - POST will checksum the FCODE proms on plug-in cards, and report the device bad when a checksum fails. Version -05 specific information: --------------------------------- CPU/Memory Board: Ultra Enterprise 3.2 Version 7 created 1997/02/04 13:27 POST 3.5.1 1997/01/30 15:29 IO Graphics Board: I/O Type 2 FCODE 1.8.1 1996/12/12 18:22 iPOST 3.4.2 1997/01/10 13:34 Dual Sbus IO Board: I/O Type 1 FCODE 1.8.1 1996/12/12 18:22 iPOST 3.4.2 1997/01/10 13:34 Bugs fixed in this release for the firmware: 1260863 2 2 XIR can cause a fatal error 1260643 E6000 OBP not masking failed component (CPU mod) fails POST Other changes/New Features/Enhancements: - Use SUNW,UltraSPARC-II instead of SUNW,UltraSPARC for BlackBird cpu-node name. - Support 4MB-ecache BlackBird modules, CPU eache-size property contains appropriate value to stand for usable ecache size. - Increase user space from 32KB to 96KB in order to support big IO configuration (It can support maximum 15 IO boards with fully plugged-in SBus or PCI cards.) - Support new PCI boards. - Support new SOC+ IO/IOG boards. - Support CPU hot-plug but disable OS interface words SUNW,shutdow-self and SUNW,wakeup-cpu. - Rmote XIR and Button XIR operation hang problem fixed. (fixed the multiple XIR master bug and changed the soft reset after the XIR to use the clock board reset to make it synchonous) - Includes support to configure new IO boards (with the SOC+ installed). - Includes support to configure larger Ecache modules. The general rules for mixing CPU modules with various ecache sizes as supported with this CPU PROM release. NOTES: 1. Don't mix UltraSparcI Modules with UltraSparcII Modules. 2. old CPU System Boards can support up to a 2Mbyte Ecache Module 3. new CPU System Boards can support up to an 8Mbyte Ecache Module 4. OBP and prtdiag only report the configured ecache size, not the actual size POST always reports the actual cache size present. UltraSparc I The general rule: Various ecache sizes, up to the maximum supported by the system board in use (2MB or 4MB), are supported in the system as long as both Modules on the system board have the same size ecache. NOTE: A 4MB UltraSparcI (if ever) requires the newer System Board. If both modules on the system board have the same size ecache, then configure for the size of ecache. If modules on the system board have different size ecache, then deconfigure the slave CPU module on that system board (usually the odd numbered module). UltraSparc II The general rule: Various ecache sizes, up to the maximum supported by the system board in use (2MB or 4MB), are supported in the system. NOTE: When a 4MB Modules is installed on older System Boards it will be configured for a cache size of 2MB. If both modules on the system board have the same size ecache, then configure for the size of ecache. If modules on the system board have different size ecache, then configure the size of the cache to be the smaller of the 2 modules ecache. Version -06 specific information: --------------------------------- CPU/Memory Board: Ultra Enterprise 3.2 Version 8 created 1997/04/10 16:26 POST 3.6.1 1997/04/17 13:37 IO Graphics Board: I/O Type 2 FCODE 1.8.1 1996/12/12 18:22 iPOST 3.4.2 1997/01/10 13:34 Dual Sbus IO Board: I/O Type 1 FCODE 1.8.1 1996/12/12 18:22 iPOST 3.4.2 1997/01/10 13:34 Dual PCI IO Board: I/O Type 3 FCODE 1.8.7 1997/05/09 11:18 iPOST 3.0.2 1997/05/01 10:56 Bugs fixed in this release for the firmware: Other changes/New Features/Enhancements: . Added functionality to support processor power control for Solaris 2.6. . Added the PCI I/O error handler to take care of Psycho, Pci_bus, onboard Cheerio, onboard Isp1040 errors passed by new POST. . Created the appropriate dummy sbus node for the broken SYSIO chip instead of probing the FCode on the IO board to create the sbus node. This fixes the Fatal Reset problem caused by probing the broken SYSIO. . Improved .xir-state-all to print valid xir states. . Resync'ed catchexc.fth with Desktop OBP to restore Forth stacks in (crestart) which is claimed to fix for L1-A bugs 1223421, 1229983, 1244597. But I still saw the L1-A bug 1229983 exists, though the change is necessary. . Updated POST error reporting mechanism to handle pci board component failures. NOTE: This is the first release version to support PCI IO boards officially. User should upgrade the system firmware with no PCI IO boards plugged in. Version -07 specific information: --------------------------------- CPU/Memory Board: CPU/Memory OBP 3.2.9 1997/07/09 13:12 POST 3.6.1 1997/04/17 13:37 Bugs fixed in this release for the firmware: 4055485 (1/1): FFB2 fails OBP 4056652 (1/1): SunFire proms have wrong parameters 4058035 (4/5): "CPU tick sync" console message when restarting a powered-off CPU Other changes/New Features/Enhancements: . Change the default value of diag-device to 'disk diskbrd diskisp disksoc net' (from 'net') due to the change of the default value of diag-switch? from false to true. NOTE: This Prom creates a dummy nvram configuration variable "dummy-config-var" in order to fix 4056652 with nvram forced to be reset to default values. This dummy variable should not be seen by user, somehow it appears when user types 'printenv'. I will fix this in next release of CPU Prom. Version -08 specific information: --------------------------------- CPU/Memory Board: CPU/Memory OBP 3.2.10 1997/09/08 13:27 POST 3.7.2 1997/09/04 09:51 SOC+ Dual Sbus IO Board: I/O Type 4 FCODE 1.8.6 1997/09/18 14:55 iPOST 3.4.4 1997/08/26 17:37 SOC+ IO Graphics Board: I/O Type 5 FCODE 1.8.6 1997/09/18 14:52 iPOST 3.4.4 1997/08/26 17:37 Bugs fixed in this release for the firmware: 4071558 (1/5): Fatal Error Reset message displays wrong year (Year 2000 compliant issue) 4073702 (2/2): E5000 hanging with messages: Fatal error Other changes/New Features/Enhancements: - Removed the dummy nvram configuration variable "dummy-config-var" created in 3.2.9 when fixed bug 4056652 (1/1) SunFire proms have wrong parameters. - Added the SOCAL WWN (World Wide Name) support. . Preserve some NVRAM area on the IO boards for WWN. . set-socal-wwn ( wwn board# -- ) to set the WWN. . .socal-wwns ( -- ) to display the WWNs if they are present in the system. - Fixed diagnostic-mode? to check the key switch position (= diag?) besides the configuration variable diag-switch?. NOTE: This is the 1st release version to support SOC+ IO/IOG boards officially. User should upgrade the system firmware with no SOC+ IO/IOG boards plugged in. For SOC+ IO/IOG Prom's: . SOC+ IO/IOG FCode (& Microcde) - New SOCAL FCode and Microcode to replace SOC FCode and Microcode in IO/IOG Prom's. (Note: socal is also called soc+, the code between socal and soc is imcompatible. i.e. Socal code doesn't work on soc device and soc code doesn't work on socal device.) . SOC+ IO/IOG POST - No change between SOC+ POST and SOC POST. - Fixed a bogus error message when the external transciever was connected to he hme. Version -09 specific information: --------------------------------- CPU/Memory Board: CPU/Memory OBP 3.2.11 1997/11/20 14:17 POST 3.7.3 1997/11/20 17:41 Dual Sbus IO Board: I/O Type 1 FCODE 1.8.3 1997/11/14 12:41 iPOST 3.4.4 1997/08/26 17:37 IO Graphics Board: I/O Type 2 FCODE 1.8.3 1997/11/14 12:41 iPOST 3.4.4 1997/08/26 17:37 SOC+ Dual Sbus IO Board: I/O Type 4 FCODE 1.8.7 1997/12/08 15:39 iPOST 3.4.4 1997/08/26 17:37 SOC+ IO Graphics Board: I/O Type 5 FCODE 1.8.7 1997/12/08 15:39 iPOST 3.4.4 1997/08/26 17:37 CPU OBP/POST ------------ Bugs fixed in this release for the firmware: 4045138 (2/3): POST fails to detect faulty 167Mhz processor 4092765 (2/3): E3000..E6000 POST hangs during fcopy operation with new Am29F040B flashprom. 4086435 (2/2): UE6000 with latest kernel/OBP patches, fails to drop to kadb. (Ported Dave Redman's fix in 3.11.18 deuterium OBP.) NOTE: The client debugger fix is incomplete, it's under developing. 4018294 (1/1): client-tte-handler not called for large addresses. Enhancements/Features/Changes: - Support all flashproms whose programming specifications/algorithms are the same as those of the AMD Am29F040. This change was required to make fcopy work with the SGS-Thomson M29F040 which has a different device id code. NOTE: OBP flash-update command, OBP fp-copy command, POST fcopy command will not work on the SGS flash Prom with version 3.2.10 (or earlier) being on the master CPU board (which is in lowest slot#). IO/IOG OBP (FCode & Microcode) ----------------------------------- Bugs fixed in this release for the Happymeal FCode resident on IO/IOG boards: - Fix my-space initialization for the SUNW,fas node, it should have the same value (3 = onboard sbus slot#) as the SUNW,hme node. Without fixing this, my-space of SUNW,fas could be 0 (or other value) depending on the system configuration, this will cause several different kinds of failures such as FDDI hanging, FAS hanging, bad slot3, or probe-scsi-all doesn't work for the FAS node etc. IO/IOG POST ------------- - Fixed a bogus error message when the external transciever was connected to the hme. SOC+ IO/SOC+ IOG OBP (FCode & Microcode) ----------------------------------- Bugs fixed in this release for the Happymeal FCode resident on all IO/IOG and SOC+ IO/IOG boards: - Fix my-space initialization for the SUNW,fas node, it should have the same value (3 = onboard sbus slot#) as the SUNW,hme node. Without fixing this, my-space of SUNW,fas could be 0 (or other value) depending on the system configuration, this will cause several different kinds of failures such as FDDI hanging, FAS hanging, bad slot3, or probe-scsi-all doesn't work for the FAS node etc. Enhancements/Features/Changes: - Newer SOC+ FCode (version 1.11) * LIP error recovery improvement for bug 4067387: fcode doesn't recover from the lip while booting from a photon disk (dual host booting problem). * Fixed the socal model property to contain the correct part number. - Changed the derivation of the WWNs of the onboard SOC+ node and its ports for a SOC+ IO/IOG board by basing on the system MAC address and its board#. The 64bit WWN format is as following: bit63-60: 2 (i.e. IEEE-extension type) bit59-54: Reserved ( 0 ) bit53-50: Board# bit49-48: Node & port id (node = 0, port0 = 1, port1 = 2) bit47-00: System MAC address E.g. ethernet address 8:0:20:8a:37:9e, SOC+ board on slot#2 The node WWN will be 20080800208a379e, the port0 WWN will be 20090800208a379e, the port1 WWN will be 200a0800208a379e. The old way is that it's derived from the number shown in the SOC+ label if it's programmed into a special location of NVRAM on the board. or it's derived from the MAC address if the number is not programmed in the NVRAM. - Fixed the flashprom model property to contain the correct part number. (The new part number was pulled out after last SOC+ IO/IOG release.) SOC+ IO/IOG POST ---------------- No change. Version 3.2.12 specific information: ------------------------------------ CPU/Memory Board: CPU/Memory OBP 3.2.12 1998/01/13 19:51 POST 3.8.4 1998/01/21 17:09 CPU OBP/POST ------------ Bugs fixed in this release for the firmware: 4041025 (2/2): single-stepping over some sethi instructions is broken 4024106 (2/1): kadb :c often causes panics 4078557 (3/3): sunfire devalias net,cdrom,disk not correct for PCI board 4088491 (2/3): Console escape sequence panics sun4u systems 4102394 (4/4): RFE to add default devaliases for FCAL internal drive for Duraflame+ system. 4102353 (3/2): hot-plug cpu/memory board, fatal reset at reboot, sunfire system Enhancements/Features/Changes: - This is the first official version to support sunfire+ platforms, sunfire DR functions and 64 bit OS. - Change the banner name from "Ultra Enterprise" to "Sun Enterprise". - Add device_type = scsi-2 support in probe-scsi-all. - Fix the wrong IO Type version display in the message "Multiple version of IO Type X proms detected". - Added support for SF+ family, E3500/4500/5500/6500. - 300, 336, 360, 400MHZ BlackBird modules. - SF+ clock board with 3rd slots bit and TRIG_CHK bit. - 100MHZ system boards. - 4, 5, 8, 16 slot centerplanes. - enhanced clock frequency algorithm adjusts to system capability: - clock board - centerplane capability - 84/90/100MHZ. - board configuration and capability - 84/100MHZ - cpu module capability - Retained backward compatibility with SF family, E3000/4000/5000/6000. - 250 MHZ BB modules and Spitfire modules - clock board - 84 MHZ system boards - centerplanes - 'Tuned' RCTIME memory parameter calculation. - RCTIME is now recalculated after 'set-sys-clk' frequency change. - 'mfg-mode=chamber' is now retained after 'set-sys-clk' frequency change. - HOT_PLUG 'hang' now avoided when POST detects partially inserted system board via SF+ clock board TRIG_CHK h/w enhancement. Sample of actual output below for system with a partially seated +IO Type 3 (PCI) board in Slot 3. > > 0,0>Hotplug Trigger Test > 0,0> ERROR: TRIG_CHK asserted in Clock Board - Hint: Board(s) may not be properly seated > 0,0>Board 0 Cross Calls Test > 0,0> Cross Calls Test > . > . > . > 0,0>POST Failed > 0,0> > 0,0> System Board Status > 0,0>----------------------------------------------------------------- > 0,0> Slot Board Status Board Type Failures > 0,0>----------------------------------------------------------------- > 0,0> 0 | Normal |+CPU/Memory | > 0,0> 1 | Normal |+IO Type 5 | > 0,0> 2 | Not installed | | > 0,0> 3 | Not installed | | > 0,0> 4 | Not installed | | > 0,0> 5 | Not installed | | > 0,0> 6 | Not installed | | > 0,0> 7 | Normal | Disk Board | > 0,0> 16 | Online/failure | Clock Board | HOTPLUG_LOGIC > 0,0>----------------------------------------------------------------- > 0,0> > - Multi-Processor Cache Coherency Test cross-call timeout problem now corrected. Sample output below showing the error which has been corrected in this release. This problem became visible with introduction of the 336MHZ modules. > 4,1>SYSTEM LEVEL TESTING > 4,1>Board 4 Cache Coherency Test > 4,1> Multi-Processor Cache Coherence Test > 4,1>ERROR: TEST=Cache Coherency,SUBTEST=Multi-Processor Cache Coherence ID=1e.1 > 4,1>Component under test: Board 4 Cache Coherency > 4,1>CPU at MID 12 did not respond to Cross Call task id 00000808 > 4,1>Deconfiguring CPU MID 12 > 4,1>Deconfiguring CPU MID 12 > 4,1>Deconfiguring CPU MID 12 > 4,1> Testing CPU MID 13 > 4,1> Testing CPU MID 16 > 4,1> Testing CPU MID 17 NOTE: Put the following line in NVRAMRC to enable DR functions in the Prom: enable-dr ( It also needs to set the nvram variable use-nvramrc? to true. ) ***IMPORTANT NOTE*** CPU prom version 3.2.9 (introduced in flash-update-07) has some nvram configuration variable changes. As a consequence of the upgrade, the system's nvram configuration variables WILL BE reset to their default values if the upgrade is from cpu prom version 3.2.8 (or lower) to 3.2.9 (or higher). There is no warning message shown during upgrade via flash-update-07, flash-update-08, flash-update-09. This is improved in flash-update-10. If the current cpu prom version is 3.2.8 (or lower), flash-update-10 will display important warning note about the change of nvram configuration variables. It will not give any warning note if the current cpu prom version is 3.2.9 (or higher). Here shows one upgrade example from 3.2.8 as following: campfire3# campfire3# ./flash-update-10 Extracting files ... Done. Loading flashprom driver ... Done. Current System Board PROM Revisions: ------------------------------------ Board 2: CPU/Memory OBP 3.2.8 1997/04/10 16:26 POST 3.6.1 1997/04/17 13:37 Board 4: CPU/Memory OBP 3.2.8 1997/04/10 16:26 POST 3.6.1 1997/04/17 13:37 Board 1: I/O Type 1 FCODE 1.8.3 1997/11/14 12:41 iPOST 3.4.4 1997/08/26 17:37 Board 6: I/O Type 2 FCODE 1.8.3 1997/11/14 12:41 iPOST 3.4.4 1997/08/26 17:37 Available 'Update' Revisions: ----------------------------- CPU/Memory OBP 3.2.12 1998/01/13 19:51 POST 3.8.4 1998/01/21 17:09 I/O Type 1 FCODE 1.8.3 1997/11/14 12:41 iPOST 3.4.4 1997/08/26 17:37 I/O Type 2 FCODE 1.8.3 1997/11/14 12:41 iPOST 3.4.4 1997/08/26 17:37 I/O Type 3 FCODE 1.8.7 1997/05/09 11:18 iPOST 3.0.2 1997/05/01 10:56 I/O Type 4 FCODE 1.8.7 1997/12/08 15:39 iPOST 3.4.4 1997/08/26 17:37 I/O Type 5 FCODE 1.8.7 1997/12/08 15:39 iPOST 3.4.4 1997/08/26 17:37 Verifying Checksums: Okay Do you wish to flash update your firmware? y/[n] : y **IMPORTANT** As a consequence of the firmware upgrade that is about to take place, it is very possible that the customized values in the configuration variables will revert to their *default values* upon the next system power-cycle or soft-reset. If this happens, it could have a significant effect on the behavior of the system after the power-cycle or soft-reset. Following is a list of the system's NVRAM configuration variables which have been customized (i.e. they are different than the default values). You may wish to write down the values of the indicated configuration variables so that they may be restored (if necessary) after the next power-cycle or soft-reset. Name: auto-boot? Current: false Default: true Name: diag-device Current: /sbus@3,0/SUNW,fas/sd@9,0:a Default: net Name: diag-switch? Current: true Default: false Are you sure you wish to continue? y/[n] :