.TITLE	MEMORY
	.IDENT	"V1.3"
;
;   Author:	D. Mischler	30-OCT-87
;
;   This module contains routines for reading and
;   writing memory in the debug environment.
;
; V1.1	D. Mischler  12-JAN-88	Major redesign.
; V1.2	D. Mischler  30-MAY-88	Trap appropriate addressing violations.
; V1.3	D. Mischler  16-NOV-88	Conditionalize simulation specific code.
; V1.4	D. Mischler  30-NOV-88	Change diagnostic from E.DAFU to E.AWMF.
;
	.PAGE
	.PSECT	CODE,I,RO
MSTART:				; Start of memory module code.

;
;   Subroutine to read the target task PC.
;
M$R.PC::
	JSR	R5,$SAVRG	; Save registers R3 - R5.
	MOV	#7*2,R5		; Get task context buffer offset.
	CALL	MAPREG		; Map register, OK?
	BCS	10$		; No, exit.
	MOV	(R1),R1		; Read PC contents.
10$:	RETURN
;
;   Subroutine to write the target task PC.
;
M$W.PC::
	CALL	$SAVAL		; Save all registers.
	MOV	R1,R4		; Copy value to be written.
	MOV	#7*2,R5		; Get task context buffer offset.
	CALL	MAPREG		; Map register, OK?
	BCS	10$		; No, exit.
	MOV	R4,(R1)		; Write PC contents.
10$:	RETURN
;
;   Subroutine to map the target task PSW.
;
M$M.PS::
	JSR	R5,$SAVRG	; Save registers R3 - R5.
	MOV	#8.*2,R5	; Get task context buffer offset.
;
;   Map a register. R5 contains task context buffer offset.
;
MAPREG:	ADD	TSKCTX,R5	; Produce register address.
	CLR	R0		; Assume registers are in data space.
	CALL	T$MAP		; Map the specified address, OK?
	BCC	10$		; Yes, exit.
	MOV	#E.AWMF,R1	; Get appropriate error code.
10$:	RETURN
	.PAGE
;
;   Subroutine to read the instruction space word pointed to by R5.
;   R5 is incremented past the word. Data is returned in R1.
;
M$RI5P::
	MOV	R0,-(SP)	; Preserve R0.
	MOV	#AS.UIS,R0	; Get desired address space code.
	BR	RDWP		; Read word and increment address.
;
;   Subroutine to read the data space word pointed to by R5.
;   R5 is incremented past the word. Data is returned in R1.
;
M$RD5P::
	MOV	R0,-(SP)	; Preserve R0.
	CLR	R0		; Get desired address space code.
RDWP:	CALL	T$MAP		; Map specified address, OK?
	BCS	10$		; No, exit with failure.
	MOV	(R1),R1		; Fetch the specified word.
	INC	R5		; Point past the word without changing carry.
	INC	R5
10$:	MOV	(SP)+,R0	; Recover saved R0.
	RETURN
;
;   Subroutine to read the data space byte pointed to by R5.
;
M$RDB5::
	MOV	R0,-(SP)	; Preserve R0.
	CLR	R0		; Get desired address space code.
	CALL	T$MAP		; Map specified address, OK?
	BCS	10$		; No, exit with failure.
	MOVB	(R1),R1		; Fetch the specified byte.
10$:	MOV	(SP)+,R0	; Recover saved R0.
	RETURN
	.PAGE
;
;   Subroutine to write an instruction word to the address in R5.
;
M$WI5::
	MOV	R0,-(SP)	; Preserve R0.
	MOV	R1,-(SP)	; Save word to be written.
	MOV	#AS.UIS,R0	; Get desired address space code.
	BR	WRTWRD		; Write word and return.
;
;   Subroutine to write a data word to the address in R5.
;
M$WD5::
	MOV	R0,-(SP)	; Preserve R0.
	MOV	R1,-(SP)	; Save word to be written.
	CLR	R0		; Get desired address space code.
WRTWRD:	CALL	T$MAP		; Map specified address, OK?
	BCS	10$		; No, exit with failure.
	MOV	(SP),(R1)	; Write the specified word.
10$:	MOV	(SP)+,R1	; Recover saved registers.
	MOV	(SP)+,R0
	RETURN


;
;   Subroutine to write a data byte to the address in R5.
;
M$WDB5::
	MOV	R0,-(SP)	; Preserve R0.
	MOV	R1,-(SP)	; Save data to be written.
	CLR	R0		; Get desired address space code.
	CALL	T$MAP		; Map specified address, OK?
	BCS	10$		; No, exit with failure.
	MOVB	(SP),(R1)	; Write the specified byte.
10$:	MOV	(SP)+,R1	; Recover saved registers.
	MOV	(SP)+,R0
	RETURN
	.PAGE
;
;   Memory Protection Violation SST entry point.
;
MPVSST::
	.IF DF	I$MTPS
	CMP	6(SP),#MSTART	; Is PC too low to be in module MEMORY?
	BLO	10$		; Yes, check for simulation.
	CMP	6(SP),#MPVSST	; Is PC too high?
	BLOS	20$		; No, set carry and exit.
10$:	TST	ABOSTK		; Is an instruction being simulated?
	BEQ	30$		; No, assume it's a bug.
	JMP	SIMABO		; Abort instruction simulation.
;   Violation occurred in module MEMORY.
20$:	ADD	#6,SP		; Ignore MMU status register images.
	BIS	#PS.C,2(SP)	; Set carry in return context.
	RTI			; Return after point of failure.
;   Violation should be passed to DBGAID.
30$:	JMP	@AIDMPV		; Must be a bug.

;
;   Odd address or other trap 4 SST entry point.
;
OAVSST::
	CMP	(SP),#MSTART	; Is PC too low to be in module MEMORY?
	BLO	10$		; Yes, check for simulation.
	CMP	(SP),#MPVSST	; Is PC too high?
	BLOS	20$		; No, set carry and exit.
10$:	TST	ABOSTK		; Is an instruction being simulated?
	BEQ	30$		; No, assume it's a bug.
	JMP	SIMABO		; Abort instruction simulation.
;   Violation occurred in module MEMORY.
20$:	BIS	#PS.C,2(SP)	; Set carry in return context.
	RTI			; Return after point of failure.
;   Violation should be passed to DBGAID.
30$:	JMP	@AIDOAV		; Must be a bug.
	.IFF	; DF I$MTPS
	CMP	6(SP),#MSTART	; Is PC too low to be in module MEMORY?
	BLO	10$		; Yes, assume it's a bug.
	CMP	6(SP),#MPVSST	; Is PC too high?
	BHI	10$		; Yes, assume it's a bug.
;   Violation occurred in module MEMORY.
	ADD	#6,SP		; Ignore MMU status register images.
	BIS	#PS.C,2(SP)	; Set carry in return context.
	RTI			; Return after point of failure.
;   Violation should be passed to DBGAID.
10$:	JMP	@AIDMPV		; Must be a bug.

;
;   Odd address or other trap 4 SST entry point.
;
OAVSST::
	CMP	(SP),#MSTART	; Is PC too low to be in module MEMORY?
	BLO	10$		; Yes, assume it's a bug.
	CMP	(SP),#MPVSST	; Is PC too high?
	BHI	10$		; Yes, assume it's a bug.
;   Violation occurred in module MEMORY.
	BIS	#PS.C,2(SP)	; Set carry in return context.
	RTI			; Return after point of failure.
;   Violation should be passed to DBGAID.
10$:	JMP	@AIDOAV		; Must be a bug.
	.ENDC	; DF I$MTPS

	.END