.TITLE OPCTBL .IDENT "V1.6" ; ; Author: D. Mischler 10-JUN-87 ; ; This module contains a table of the PDP-11 opcodes, ; their associated mnemonics and type/class info. ; A table of register mnemonics and some read-only ; ASCII text is also included here. ; .PAGE ; ; Opcode class and decode mask definitions. The high 4 bits ; are the opcode class, the low 12 bits mask out variable ; fields. Note that the class number for immediate operands ; is the number of bits used to encode the operand, and that ; a resulting class word of zero may not be used (terminator). ; CL = 4096. ; Class field multiplier. BRANCH = 0*CL+000377 ; Branch instruction with 8-bit offset. COND = 1*CL+000017 ; Condition code instructions. DOUBLE = 2*CL+007777 ; Double operand with any addressing modes. IMM3 = 3*CL+000007 ; 3-bit immediate operand. FPADST = 4*CL+000377 ; Floating point accumulator destination. FPASRC = 5*CL+000377 ; Floating point accumulator source. IMM6 = 6*CL+000077 ; 6-bit immediate operand. NONE = 7*CL+000000 ; No operands. IMM8 = 10*CL+000377 ; 8-bit immediate operand. REG = 11*CL+000007 ; Single register operand. REGDST = 12*CL+000777 ; Register destination with any source mode. REGSRC = 13*CL+000777 ; Register source with any destination mode. SINGLE = 14*CL+000077 ; Single operand with any addressing mode. SOB = 15*CL+000777 ; Subtract one and branch. ; ; Macro to generate an opcode table entry. ; .MACRO OPCODE MNEMON,CLASS,VALUE .WORD CLASS $$$ =. .WORD 0,0 .= $$$ .RAD50 "MNEMON" .= $$$+4 .WORD VALUE .ENDM OPCODE ; ; Opcode table entry offset definitions. ; .ASECT .= 0 OP.CLS::.BLKW 1 ; Opcode class and decode mask. OP.MNE::.BLKW 2 ; Opcode mnemonic in RAD50. OP.VAL::.BLKW 1 ; Opcode value. OP.LEN:: .PAGE .PSECT $OPTBL,D,RO ; ; The actual opcode table (in all its blinding glory). This ; table must be scanned linearly during disassembly because ; the mnemonics for some instructions are ordered by ; preference (e.g. BCC is preferred to BHIS). Only the first ; mnemonic for FPP floating point instructions appears (e.g. ; LDF is present, but LDD is not). The table entry order is ; based on dynamic and static instruction frequency, as well ; as the previously discussed preferences. ; OPCTBL:: ; Most commonly used instructions. OPCODE MOV, DOUBLE, 010000 OPCODE BEQ, BRANCH, 001400 OPCODE CALL, SINGLE, 004700 OPCODE BNE, BRANCH, 001000 OPCODE CMP, DOUBLE, 020000 OPCODE RETURN, NONE, 000207 OPCODE ADD, DOUBLE, 060000 OPCODE MOVB, DOUBLE, 110000 OPCODE CMPB, DOUBLE, 120000 OPCODE TST, SINGLE, 005700 OPCODE BCS, BRANCH, 103400 OPCODE CLR, SINGLE, 005000 OPCODE INC, SINGLE, 005200 OPCODE SUB, DOUBLE, 160000 OPCODE BITB, DOUBLE, 130000 OPCODE DEC, SINGLE, 005300 OPCODE BCC, BRANCH, 103000 OPCODE TSTB, SINGLE, 105700 OPCODE BISB, DOUBLE, 150000 OPCODE ASL, SINGLE, 006300 OPCODE SOB, SOB, 077000 OPCODE BIC, DOUBLE, 040000 OPCODE BIS, DOUBLE, 050000 OPCODE BIT, DOUBLE, 030000 OPCODE JMP, SINGLE, 000100 ; Basic instructions. OPCODE ADC, SINGLE, 005500 OPCODE ADCB, SINGLE, 105500 OPCODE ASLB, SINGLE, 106300 OPCODE ASR, SINGLE, 006200 OPCODE ASRB, SINGLE, 106200 OPCODE BGE, BRANCH, 002000 OPCODE BGT, BRANCH, 003000 OPCODE BHI, BRANCH, 101000 OPCODE BICB, DOUBLE, 140000 OPCODE BLE, BRANCH, 003400 OPCODE BLOS, BRANCH, 101400 OPCODE BLT, BRANCH, 002400 OPCODE BMI, BRANCH, 100400 OPCODE BPL, BRANCH, 100000 OPCODE BR, BRANCH, 000400 OPCODE BVC, BRANCH, 102000 OPCODE BVS, BRANCH, 102400 OPCODE CCC, NONE, 000257 OPCODE CLRB, SINGLE, 105000 OPCODE COM, SINGLE, 005100 OPCODE COMB, SINGLE, 105100 OPCODE DECB, SINGLE, 105300 OPCODE INCB, SINGLE, 105200 OPCODE JSR, REGSRC, 004000 OPCODE NEG, SINGLE, 005400 OPCODE NEGB, SINGLE, 005400 OPCODE NOP, NONE, 000240 OPCODE ROL, SINGLE, 006100 OPCODE ROLB, SINGLE, 106100 OPCODE RORB, SINGLE, 106000 OPCODE ROR, SINGLE, 006000 OPCODE RTS, REG, 000200 OPCODE SBC, SINGLE, 005600 OPCODE SBCB, SINGLE, 105600 OPCODE SCC, NONE, 000277 OPCODE SWAB, SINGLE, 000300 ; Extended integer instructions. OPCODE ASH, REGDST, 072000 OPCODE ASHC, REGDST, 073000 OPCODE DIV, REGDST, 071000 OPCODE MUL, REGDST, 070000 OPCODE SXT, SINGLE, 006700 OPCODE XOR, REGSRC, 074000 ; Traps, privileged, processor specific, and other rarities. OPCODE BHIS, BRANCH, 103000 OPCODE BLO, BRANCH, 103400 OPCODE BPT, NONE, 000003 OPCODE CALLR, SINGLE, 000100 ; CALLR must appear after JMP. CLOPC:: OPCODE CL, COND, 000240 ; CL must appear after NOP. OPCODE CSM, SINGLE, 007000 OPCODE EMT, IMM8, 104000 OPCODE HALT, NONE, 000000 OPCODE IOT, NONE, 000004 OPCODE MARK, IMM6, 006400 OPCODE MFPD, SINGLE, 106500 OPCODE MFPI, SINGLE, 006500 OPCODE MFPS, SINGLE, 106700 OPCODE MFPT, NONE, 000007 OPCODE MTPD, SINGLE, 106600 OPCODE MTPI, SINGLE, 006600 OPCODE MTPS, SINGLE, 106400 OPCODE RESET, NONE, 000005 OPCODE RTI, NONE, 000002 OPCODE RTT, NONE, 000006 SEOPC:: OPCODE SE, COND, 000260 OPCODE SPL, IMM3, 000230 OPCODE TRAP, IMM8, 104400 OPCODE TSTSET, SINGLE, 007200 OPCODE WAIT, NONE, 000001 OPCODE WRTLCK, SINGLE, 007300 .IF DF I$FPP ; Floating point processor instructions (FPP). OPCODE ABSF, SINGLE, 170600 OPCODE ADDF, FPADST, 172000 OPCODE CFCC, NONE, 170000 OPCODE CLRF, SINGLE, 170400 OPCODE CMPF, FPADST, 173400 OPCODE DIVF, FPADST, 174400 OPCODE LDCFD, FPADST, 177400 OPCODE LDCIF, FPADST, 177000 OPCODE LDEXP, FPADST, 176400 OPCODE LDF, FPADST, 172400 OPCODE LDFPS, SINGLE, 170100 OPCODE MODF, FPADST, 171400 OPCODE MULF, FPADST, 171000 OPCODE NEGF, SINGLE, 170700 OPCODE SETD, NONE, 170011 OPCODE SETF, NONE, 170001 OPCODE SETI, NONE, 170002 OPCODE SETL, NONE, 170012 OPCODE STCFD, FPASRC, 176000 OPCODE STCFI, FPASRC, 175400 OPCODE STEXP, FPASRC, 175000 OPCODE STF, FPASRC, 174000 OPCODE STFPS, SINGLE, 170200 OPCODE STST, SINGLE, 170300 OPCODE SUBF, FPADST, 173000 OPCODE TSTF, SINGLE, 170500 .ENDC ; I$FPP .IF DF I$FIS ; Floating instruction set (FIS). OPCODE FADD, REG, 075000 OPCODE FDIV, REG, 075030 OPCODE FMUL, REG, 075020 OPCODE FSUB, REG, 075010 .ENDC ; I$FIS .WORD 0 ; Table terminator. .PAGE ; ; Register mnemonic table. ; REGTBL:: .WORD "R0 .WORD "R1 .WORD "R2 .WORD "R3 .WORD "R4 .WORD "R5 .WORD "SP .WORD "PC .WORD 0 .END