.TITLE SIM11 .IDENT "V1.6" .NLIST BEX,CND ; ; Author: D. Mischler 10-FEB-88 ; ; This module simulates the execution of common instructions. ; This significantly increases the speed of single stepping. ; ; V1.1 D. Mischler ??-APR-88 Reduce target task context mapping. ; V1.2 D. Mischler 01-JUL-88 Optimize simulated register loading. ; V1.3 D. Mischler 16-NOV-88 Reduce simulation overhead. ; V1.4 D. Mischler 20-NOV-88 Collect instruction history data. ; V1.5 D. Mischler 22-NOV-88 Simulate SWAB. ; V1.6 D. Mischler 30-NOV-88 Limit consecutive simulated instructions. ; .IF NDF .RTS .CLR = CLR ; Clear base opcode. .CLRB = CLRB ; Clear byte base opcode. .JMP = JMP ; Jump base opcode. .RTS = RTS ; Return from subroutine base opcode. .SWAB = SWAB ; Swap bytes base opcode. .ENDC .IF DF I$MTPS .PSECT DATA,D,RW ; ; Data definitions. ; INSBUF: .BLKW 3 ; Simulated instruction words. INSPTR: .BLKW 1 ; Instruction buffer pointer. .PAGE .PSECT RODATA,D,RO ; ; Dispatch table for high 8 bits of opcode word. ; HI8TBL: .WORD LOWINS ; 0000XX - Miscellaneous, JMP, RTS, SPL, CLx, SEx, SWAB .WORD BRANCH ; 0004XX - BR .WORD BNE ; 0010XX - BNE .WORD BEQ ; 0014XX - BEQ .WORD BGE ; 0020XX - BGE .WORD BLT ; 0024XX - BLT .WORD BGT ; 0030XX - BGT .WORD BLE ; 0034XX - BLE .WORD JSR ; 0040XX - JSR .WORD JSR ; 0044XX - JSR .WORD SINGLW ; 0050XX - CLR, COM, INC, DEC .WORD SINGLW ; 0054XX - NEG, ADC, SBC, TST .WORD SINGLW ; 0060XX - ROR, ROL, ASR, ASL .WORD .ABORT ; 0064XX - MARK, MFPI, MTPI, SXT .WORD .ABORT ; 0070XX - CSM, Undefined, TSTSET, WRTLCK .WORD .ABORT ; 0074XX - Undefined. .WORD MOV ; 0100XX - MOV .WORD MOV ; 0104XX - MOV .WORD MOV ; 0110XX - MOV .WORD MOV ; 0114XX - MOV .WORD MOV ; 0120XX - MOV .WORD MOV ; 0124XX - MOV .WORD MOV ; 0130XX - MOV .WORD MOV ; 0134XX - MOV .WORD MOV ; 0140XX - MOV .WORD MOV ; 0144XX - MOV .WORD MOV ; 0150XX - MOV .WORD MOV ; 0154XX - MOV .WORD MOV ; 0160XX - MOV .WORD MOV ; 0164XX - MOV .WORD MOV ; 0170XX - MOV .WORD MOV ; 0174XX - MOV .WORD CMP ; 0200XX - CMP .WORD CMP ; 0204XX - CMP .WORD CMP ; 0210XX - CMP .WORD CMP ; 0214XX - CMP .WORD CMP ; 0220XX - CMP .WORD CMP ; 0224XX - CMP .WORD CMP ; 0230XX - CMP .WORD CMP ; 0234XX - CMP .WORD CMP ; 0240XX - CMP .WORD CMP ; 0244XX - CMP .WORD CMP ; 0250XX - CMP .WORD CMP ; 0254XX - CMP .WORD CMP ; 0260XX - CMP .WORD CMP ; 0264XX - CMP .WORD CMP ; 0270XX - CMP .WORD CMP ; 0274XX - CMP .WORD BIT ; 0300XX - BIT .WORD BIT ; 0304XX - BIT .WORD BIT ; 0310XX - BIT .WORD BIT ; 0314XX - BIT .WORD BIT ; 0320XX - BIT .WORD BIT ; 0324XX - BIT .WORD BIT ; 0330XX - BIT .WORD BIT ; 0334XX - BIT .WORD BIT ; 0340XX - BIT .WORD BIT ; 0344XX - BIT .WORD BIT ; 0350XX - BIT .WORD BIT ; 0354XX - BIT .WORD BIT ; 0360XX - BIT .WORD BIT ; 0364XX - BIT .WORD BIT ; 0370XX - BIT .WORD BIT ; 0374XX - BIT .WORD BIC ; 0400XX - BIC .WORD BIC ; 0404XX - BIC .WORD BIC ; 0410XX - BIC .WORD BIC ; 0414XX - BIC .WORD BIC ; 0420XX - BIC .WORD BIC ; 0424XX - BIC .WORD BIC ; 0430XX - BIC .WORD BIC ; 0434XX - BIC .WORD BIC ; 0440XX - BIC .WORD BIC ; 0444XX - BIC .WORD BIC ; 0450XX - BIC .WORD BIC ; 0454XX - BIC .WORD BIC ; 0460XX - BIC .WORD BIC ; 0464XX - BIC .WORD BIC ; 0470XX - BIC .WORD BIC ; 0474XX - BIC .WORD BIS ; 0500XX - BIS .WORD BIS ; 0504XX - BIS .WORD BIS ; 0510XX - BIS .WORD BIS ; 0514XX - BIS .WORD BIS ; 0520XX - BIS .WORD BIS ; 0524XX - BIS .WORD BIS ; 0530XX - BIS .WORD BIS ; 0534XX - BIS .WORD BIS ; 0540XX - BIS .WORD BIS ; 0544XX - BIS .WORD BIS ; 0550XX - BIS .WORD BIS ; 0554XX - BIS .WORD BIS ; 0560XX - BIS .WORD BIS ; 0564XX - BIS .WORD BIS ; 0570XX - BIS .WORD BIS ; 0574XX - BIS .WORD ADD ; 0600XX - ADD .WORD ADD ; 0604XX - ADD .WORD ADD ; 0610XX - ADD .WORD ADD ; 0614XX - ADD .WORD ADD ; 0620XX - ADD .WORD ADD ; 0624XX - ADD .WORD ADD ; 0630XX - ADD .WORD ADD ; 0634XX - ADD .WORD ADD ; 0640XX - ADD .WORD ADD ; 0644XX - ADD .WORD ADD ; 0650XX - ADD .WORD ADD ; 0654XX - ADD .WORD ADD ; 0660XX - ADD .WORD ADD ; 0664XX - ADD .WORD ADD ; 0670XX - ADD .WORD ADD ; 0674XX - ADD .WORD .ABORT ; 0700XX - MUL .WORD .ABORT ; 0704XX - MUL .WORD .ABORT ; 0710XX - DIV .WORD .ABORT ; 0714XX - DIV .WORD .ABORT ; 0720XX - ASH .WORD .ABORT ; 0724XX - ASH .WORD .ABORT ; 0730XX - ASHC .WORD .ABORT ; 0734XX - ASHC .WORD .ABORT ; 0740XX - XOR .WORD .ABORT ; 0744XX - XOR .WORD .ABORT ; 0750XX - FIS, Undefined .WORD .ABORT ; 0754XX - Undefined .WORD .ABORT ; 0760XX - Undefined .WORD .ABORT ; 0764XX - Undefined .WORD SOB ; 0770XX - SOB .WORD SOB ; 0774XX - SOB .WORD BPL ; 1000XX - BPL .WORD BMI ; 1004XX - BMI .WORD BHI ; 1010XX - BHI .WORD BLOS ; 1014XX - BLOS .WORD .ABORT ; 1020XX - BVC .WORD .ABORT ; 1024XX - BVS .WORD BCC ; 1030XX - BCC, BHIS .WORD BCS ; 1034XX - BCS, BLO .WORD .ABORT ; 1040XX - EMT .WORD .ABORT ; 1044XX - TRAP .WORD SINGLB ; 1050XX - CLRB, COMB, INCB, DECB .WORD SINGLB ; 1054XX - NEGB, ADCB, SBCB, TSTB .WORD SINGLB ; 1060XX - RORB, ROLB, ASRB, ASLB .WORD .ABORT ; 1064XX - MTPS, MFPD, MTPD, MFPS .WORD .ABORT ; 1070XX - Undefined .WORD .ABORT ; 1074XX - Undefined .WORD MOVB ; 1100XX - MOVB .WORD MOVB ; 1104XX - MOVB .WORD MOVB ; 1110XX - MOVB .WORD MOVB ; 1114XX - MOVB .WORD MOVB ; 1120XX - MOVB .WORD MOVB ; 1124XX - MOVB .WORD MOVB ; 1130XX - MOVB .WORD MOVB ; 1134XX - MOVB .WORD MOVB ; 1140XX - MOVB .WORD MOVB ; 1144XX - MOVB .WORD MOVB ; 1150XX - MOVB .WORD MOVB ; 1154XX - MOVB .WORD MOVB ; 1160XX - MOVB .WORD MOVB ; 1164XX - MOVB .WORD MOVB ; 1170XX - MOVB .WORD MOVB ; 1174XX - MOVB .WORD CMPB ; 1200XX - CMPB .WORD CMPB ; 1204XX - CMPB .WORD CMPB ; 1210XX - CMPB .WORD CMPB ; 1214XX - CMPB .WORD CMPB ; 1220XX - CMPB .WORD CMPB ; 1224XX - CMPB .WORD CMPB ; 1230XX - CMPB .WORD CMPB ; 1234XX - CMPB .WORD CMPB ; 1240XX - CMPB .WORD CMPB ; 1244XX - CMPB .WORD CMPB ; 1250XX - CMPB .WORD CMPB ; 1254XX - CMPB .WORD CMPB ; 1260XX - CMPB .WORD CMPB ; 1264XX - CMPB .WORD CMPB ; 1270XX - CMPB .WORD CMPB ; 1274XX - CMPB .WORD BITB ; 1300XX - BITB .WORD BITB ; 1304XX - BITB .WORD BITB ; 1310XX - BITB .WORD BITB ; 1314XX - BITB .WORD BITB ; 1320XX - BITB .WORD BITB ; 1324XX - BITB .WORD BITB ; 1330XX - BITB .WORD BITB ; 1334XX - BITB .WORD BITB ; 1340XX - BITB .WORD BITB ; 1344XX - BITB .WORD BITB ; 1350XX - BITB .WORD BITB ; 1354XX - BITB .WORD BITB ; 1360XX - BITB .WORD BITB ; 1364XX - BITB .WORD BITB ; 1370XX - BITB .WORD BITB ; 1374XX - BITB .WORD BICB ; 1400XX - BICB .WORD BICB ; 1404XX - BICB .WORD BICB ; 1410XX - BICB .WORD BICB ; 1414XX - BICB .WORD BICB ; 1420XX - BICB .WORD BICB ; 1424XX - BICB .WORD BICB ; 1430XX - BICB .WORD BICB ; 1434XX - BICB .WORD BICB ; 1440XX - BICB .WORD BICB ; 1444XX - BICB .WORD BICB ; 1450XX - BICB .WORD BICB ; 1454XX - BICB .WORD BICB ; 1460XX - BICB .WORD BICB ; 1464XX - BICB .WORD BICB ; 1470XX - BICB .WORD BICB ; 1474XX - BICB .WORD BISB ; 1500XX - BISB .WORD BISB ; 1504XX - BISB .WORD BISB ; 1510XX - BISB .WORD BISB ; 1514XX - BISB .WORD BISB ; 1520XX - BISB .WORD BISB ; 1524XX - BISB .WORD BISB ; 1530XX - BISB .WORD BISB ; 1534XX - BISB .WORD BISB ; 1540XX - BISB .WORD BISB ; 1544XX - BISB .WORD BISB ; 1550XX - BISB .WORD BISB ; 1554XX - BISB .WORD BISB ; 1560XX - BISB .WORD BISB ; 1564XX - BISB .WORD BISB ; 1570XX - BISB .WORD BISB ; 1574XX - BISB .WORD SUB ; 1600XX - SUB .WORD SUB ; 1604XX - SUB .WORD SUB ; 1610XX - SUB .WORD SUB ; 1614XX - SUB .WORD SUB ; 1620XX - SUB .WORD SUB ; 1624XX - SUB .WORD SUB ; 1630XX - SUB .WORD SUB ; 1634XX - SUB .WORD SUB ; 1640XX - SUB .WORD SUB ; 1644XX - SUB .WORD SUB ; 1650XX - SUB .WORD SUB ; 1654XX - SUB .WORD SUB ; 1660XX - SUB .WORD SUB ; 1664XX - SUB .WORD SUB ; 1670XX - SUB .WORD SUB ; 1674XX - SUB .WORD .ABORT ; 1700XX - FPP .WORD .ABORT ; 1704XX - FPP .WORD .ABORT ; 1710XX - FPP .WORD .ABORT ; 1714XX - FPP .WORD .ABORT ; 1720XX - FPP .WORD .ABORT ; 1724XX - FPP .WORD .ABORT ; 1730XX - FPP .WORD .ABORT ; 1734XX - FPP .WORD .ABORT ; 1740XX - FPP .WORD .ABORT ; 1744XX - FPP .WORD .ABORT ; 1750XX - FPP .WORD .ABORT ; 1754XX - FPP .WORD .ABORT ; 1760XX - FPP .WORD .ABORT ; 1764XX - FPP .WORD .ABORT ; 1770XX - FPP .WORD .ABORT ; 1774XX - FPP ; ; General addressing mode dispatch table. ; MODTBL: .WORD M.REG ; 00 - R0 .WORD M.REG ; 01 - R1 .WORD M.REG ; 02 - R2 .WORD M.REG ; 03 - R3 .WORD M.REG ; 04 - R4 .WORD M.REG ; 05 - R5 .WORD M.REG ; 06 - SP .WORD M.REG ; 07 - PC .WORD M.REDF ; 10 - (R0) .WORD M.REDF ; 11 - (R1) .WORD M.REDF ; 12 - (R2) .WORD M.REDF ; 13 - (R3) .WORD M.REDF ; 14 - (R4) .WORD M.REDF ; 15 - (R5) .WORD M.REDF ; 16 - (SP) .WORD .ABORT ; 17 - (PC) .WORD M.AINC ; 20 - (R0)+ .WORD M.AINC ; 21 - (R1)+ .WORD M.AINC ; 22 - (R2)+ .WORD M.AINC ; 23 - (R3)+ .WORD M.AINC ; 24 - (R4)+ .WORD M.AINC ; 25 - (R5)+ .WORD M.AISP ; 26 - (SP)+ .WORD M.IMM ; 27 - (PC)+ or #immediate .WORD M.AIDF ; 30 - @(R0)+ .WORD M.AIDF ; 31 - @(R1)+ .WORD M.AIDF ; 32 - @(R2)+ .WORD M.AIDF ; 33 - @(R3)+ .WORD M.AIDF ; 34 - @(R4)+ .WORD M.AIDF ; 35 - @(R5)+ .WORD M.AIDF ; 36 - @(SP)+ .WORD M.ABS ; 37 - @(PC)+ or @#absolute .WORD M.ADEC ; 40 - -(R0) .WORD M.ADEC ; 41 - -(R1) .WORD M.ADEC ; 42 - -(R2) .WORD M.ADEC ; 43 - -(R3) .WORD M.ADEC ; 44 - -(R4) .WORD M.ADEC ; 45 - -(R5) .WORD M.ADSP ; 46 - -(SP) .WORD .ABORT ; 47 - -(PC) .WORD .ABORT ; 50 - @-(R0) .WORD .ABORT ; 51 - @-(R1) .WORD .ABORT ; 52 - @-(R2) .WORD .ABORT ; 53 - @-(R3) .WORD .ABORT ; 54 - @-(R4) .WORD .ABORT ; 55 - @-(R5) .WORD .ABORT ; 56 - @-(SP) .WORD .ABORT ; 57 - @-(PC) .WORD M.INDX ; 60 - index(R0) .WORD M.INDX ; 61 - index(R1) .WORD M.INDX ; 62 - index(R2) .WORD M.INDX ; 63 - index(R3) .WORD M.INDX ; 64 - index(R4) .WORD M.INDX ; 65 - index(R5) .WORD M.INDX ; 66 - index(SP) .WORD M.INDX ; 67 - index(PC) .WORD M.INDF ; 70 - @index(R0) .WORD M.INDF ; 71 - @index(R1) .WORD M.INDF ; 72 - @index(R2) .WORD M.INDF ; 73 - @index(R3) .WORD M.INDF ; 74 - @index(R4) .WORD M.INDF ; 75 - @index(R5) .WORD M.INDF ; 76 - @index(SP) .WORD M.INDF ; 77 - @index(PC) ; ; Tables of operation routine addresses for single operand instructions. ; SGBTBL: .WORD CLRB,COMB,INCB,DECB,NEGB,ADCB,SBCB,TSTB,RORB,ROLB,ASRB,ASLB SGWTBL: .WORD CLR,COM,INC,DEC,NEG,ADC,SBC,TST,ROR,ROL,ASR,ASL .PAGE .PSECT CODE,I,RO ; ; Routine to simulate one PDP-11 instruction. ; On exit: Carry set if instruction cannot be simulated. ; R0 will contain the opcode word. ; SIM11:: CLR INSBUF ; Set up default abort opcode. MOV SP,ABOSTK ; Set incoming stack address for abort. ; Copy registers for fast access. TST SIMVLD ; Are simulated registers already valid? BNE 30$ ; Yes, don't read them again. DEC SIMVLD ; Indicate simulated registers are valid. MOV TSKCTX,R5 ; Get address of target task registers. MOV #SIM.R0,R4 ; Point to register save area. MOV #9.,R3 ; Get number of registers to copy. MOV #77,R2 ; Get bit mask for address block offset. 10$: CLR R0 ; Force data space access. CALL T$MAP ; Map to target task context. MOV #2,R0 ; Get address offset between two words. 20$: MOV (R1)+,(R4)+ ; Copy a register value. ADD R0,R5 ; Update target task address. DEC R3 ; Have all registers been copied? BEQ 30$ ; Yes, see if history is enabled. BIT R2,R1 ; Was a block boundary just crossed? BNE 20$ ; No, do not remap. BR 10$ ; Map task context again. ; Collect instruction history if enabled. 30$: MOV HSTPTR,R0 ; Get history buffer pointer, zero? BEQ 50$ ; Yes, fetch instruction words. MOV #SIM.R0,R1 ; Point to simulated task registers. MOV (R1)+,(R0)+ ; Copy registers to history buffer. MOV (R1)+,(R0)+ MOV (R1)+,(R0)+ MOV (R1)+,(R0)+ MOV (R1)+,(R0)+ MOV (R1)+,(R0)+ MOV (R1)+,(R0)+ MOV (R1)+,(R0)+ MOV (R1)+,(R0)+ CMP R0,HSTEND ; Reached end of history buffer? BLO 40$ ; No, no adjustment is needed. MOV HSTBUF,R0 ; Reset pointer to start of buffer. 40$: MOV R0,HSTPTR ; Save updated history buffer pointer. .PAGE ; ; Fetch next 3 instruction words (also for fast access). ; 50$: MOV SIM.PC,R5 ; Get target task PC. MOV #INSBUF,R4 ; Point to instruction area. MOV #3,R3 ; Set up loop count. 60$: MOV #AS.UIS,R0 ; Force instruction space access. CALL T$MAP ; Map to target task instruction stream. MOV #2,R0 ; Get address offset between two words. 70$: MOV (R1)+,(R4)+ ; Copy an instruction word. ADD R0,R5 ; Update target task address. DEC R3 ; Have all words been copied? BEQ 80$ ; Yes, make sure simulation is enabled. BIT R2,R1 ; Was a block boundary just crossed? BNE 70$ ; No, do not remap. BR 60$ ; Map task instruction stream again. ; Make sure simulation is enabled before proceeding. 80$: TST SIMENB ; Is instruction simulation enabled? BEQ SIMABO ; No, get opcode and exit. DEC SIMCNT ; Maximum consecutive simulations reached? BEQ SIMABO ; Yes, single-step target task. ; Call appropriate instruction simulation routine based on opcode. ; R4 will contain the opcode word on entry to the simulation routine. MOV #INSBUF,R5 ; Get instruction word address. MOV (R5)+,R4 ; Fetch instruction word. MOV R5,INSPTR ; Save instruction buffer pointer. ADD R0,SIM.PC ; Point simulated PC after instruction. MOV R4,R1 ; Duplicate opcode word. CLRB R1 ; Zero low byte. SWAB R1 ; Make high byte into a word index. ASL R1 CALL @HI8TBL(R1) ; Dispatch on upper 8 bits of opcode. .PAGE ; ; Here when instruction simulation is complete. ; MOV TSKCTX,R5 ; Get address of target task registers. MOV #SIM.R0,R4 ; Point to (modified) simulated registers. MOV #9.,R3 ; Get number of words to be copied. MOV #77,R2 ; Get bit mask for address block offset. 90$: CLR R0 ; Force data space access. CALL T$MAP ; Map to target task context. MOV #2,R0 ; Get address offset between two words. 100$: MOV (R4)+,(R1)+ ; Write a (possibly modified) register back. ADD R0,R5 ; Update target task address. DEC R3 ; Have all registers been copied? BEQ 110$ ; Yes, exit (simulation is complete). BIT R2,R1 ; Was a block boundary just crossed? BNE 100$ ; No, do not remap. BR 90$ ; Map task context again. 110$: CLR ABOSTK ; Indicate no simulation is in progress. RETURN ; ; Here if an instruction simulation must be aborted. ; SIMABO:: .ABORT: MOV ABOSTK,SP ; Restore incoming stack address. CLR ABOSTK ; Indicate no simulation is in progress. CLR SIMVLD ; Indicate simulated registers are invalid. MOV #MAXSIM,SIMCNT ; Reset maximum consecutive simulations. MOV INSBUF,R0 ; Get opcode word for exit. SEC ; Indicate instruction cannot be simulated. RETURN .PAGE ; ; Subroutine to map the destination operand. ; On entry: R4 contains the opcode word, R2 contains the operation size. ; DSTMAP: CALL DSTADR ; Get destination address and space. ; ; Routine to map a simulated address. ; On entry: R5 contains address, R0 contains address space. ; MAPADR: TST R0 ; Is address in target task? BMI 20$ ; No, just return it. Is address in D space? BNE 10$ ; No, go ahead and map it. CMP #$DSW,R5 ; Is this an attempt to access the $DSW? BNE 10$ ; No, go ahead and map it. MOV #TC.DSW,R5 ; Get task context offset to $DSW. ADD TSKCTX,R5 ; Get address of saved $DSW. 10$: CALL T$MAP ; Map destination address, OK? BCS .ABORT ; No, abort. RETURN ; Address space indicates desired value is in debugger task. 20$: MOV R5,R1 ; Copy address into place. RETURN ; ; Subroutine to get the destination operand address and space. ; On entry: R4 contains the opcode word, R2 contains operation size. ; On exit: R5 contains address, R0 contains address space code. ; DSTADR: BIC #^C<77>,R4 ; Mask opcode word to mode and register. ASL R4 ; Make it a word offset. MOV R4,R5 ; Copy it. BIC #^C<16>,R5 ; Mask copy to register index only. ADD #SIM.R0,R5 ; Get simulated register address. MOV #-1,R0 ; Indicate address is in debugger task. CALLR @MODTBL(R4) ; Dispatch on mode and register. .PAGE ; ; Handle register deferred addressing. ; M.REDF: CALL MAPADR ; Map register. MOV (R1),R5 ; Fetch register contents. CLR R0 ; Assume data space access next. M.REG: RETURN ; ; Handle Auto-Increment Deferred addressing (except for PC). ; M.AIDF: CALL M.AISP ; Defer through and adjust register. BR M.REDF ; Defer through fetched word. ; ; Handle PC Auto-Increment Deferred addressing (absolute mode). ; M.ABS: CALL M.IMM ; Get immediate value. BR M.REDF ; Defer through it. ; ; Handle Indexed Deferred addressing. ; M.INDF: CALL M.INDX ; Get indexed address. BR M.REDF ; Defer through it. ; ; Handle Auto-Decrement addressing (except SP & PC). ; M.ADEC: CALL M.REDF ; Defer through the register. SUB R2,R5 ; Adjust register by operand size. MOV R5,(R1) ; Write adjusted value back. RETURN ; ; Handle SP Auto-Decrement addressing. ; M.ADSP: CALL M.REDF ; Defer through the register. SUB #2,R5 ; Adjust SP word aligned. MOV R5,(R1) ; Write adjusted value back. RETURN .PAGE ; ; Handle Auto-Increment addressing (except SP & PC). ; M.AINC: CALL M.REDF ; Defer through the register. ADD R2,(R1) ; Adjust register by operand size. RETURN ; ; Handle SP Auto-Increment addressing. ; M.AISP: CALL M.REDF ; Defer through register. ADD #2,(R1) ; Adjust register word aligned. RETURN ; ; Handle PC Auto-Increment addressing (immediate mode). ; M.IMM: MOV INSPTR,R5 ; Get address of next instruction word. MOV #-2,R0 ; Indicate operand is in debugger task. SUB R0,INSPTR ; Point past it (SUB #-2 == ADD #2). SUB R0,SIM.PC ; Update PC past operand. RETURN ; ; Handle Indexed addressing. ; M.INDX: MOV R5,-(SP) ; Save index register address. CALL M.IMM ; Point to index constant word. MOV (R5),R5 ; Get index constant word. ADD @(SP)+,R5 ; Form actual operand address. CLR R0 ; Force data space access. RETURN .PAGE ; ; Subroutine to fetch a byte source operand in R3. ; On entry: R4 contains opcode word. ; SRCBYT: MOV R4,-(SP) ; Save opcode word. MOV #1,R2 ; Get operation size. ASL R4 ; Put source mode and register in position. ASL R4 SWAB R4 CALL DSTMAP ; Map the source operand. MOVB (R1),R3 ; Fetch the source operand (sign extends). MOV (SP)+,R4 ; Recover opcode word. RETURN ; ; Subroutine to fetch a word source operand in R3. ; On entry: R4 contains opcode word. ; SRCWRD: MOV R4,-(SP) ; Save opcode word. MOV #2,R2 ; Get operation size. ASL R4 ; Put source mode and register in position. ASL R4 SWAB R4 CALL DSTMAP ; Map the source operand. MOV (R1),R3 ; Fetch the source operand. MOV (SP)+,R4 ; Recover opcode word. RETURN .PAGE ; ; Simulate the low-order opcodes. ; LOWINS: MOV R4,R0 ; Copy opcode word. BIC #7,R0 ; Zap register number. CMP #.RTS,R0 ; Is opcode RTS? BEQ RTS ; Yes, simulate it. BIC #77,R0 ; Mask off destination mode and register. CMP #.JMP,R0 ; Is opcode JMP? BEQ JMP ; Yes, simulate it. CMP #.SWAB,R0 ; Is opcode SWAB? BEQ SWAB ; Yes, simulate it. SUB #240,R4 ; Subtract lowest condition code opcode. CMP R4,#20 ; Clear condition code bit(s)? BLO CLX ; Yes, simulate it. CMP R4,#40 ; Set condition code bit(s)? BLO SEX ; Yes, simulate it. JMP .ABORT ; ; Simulate the RTS instruction. ; RTS: BIC #^C<7>,R4 ; Keep only the register number. ASL R4 ; Make it a word index. ADD #SIM.R0,R4 ; Point to linkage register. MOV (R4),SIM.PC ; Copy linkage register to PC. MOV SIM.SP,R5 ; Get stack pointer. CALL M$RD5P ; Pop linkage word from stack. MOV R5,SIM.SP ; Save updated stack pointer. MOV R1,(R4) ; Save popped word in linkage register. RETURN ; ; Simulate the JMP instruction. ; JMP: MOV #2,R2 ; Get operation size. CALL DSTADR ; Get target address. MOV R5,SIM.PC ; Save it in the PC. RETURN ; ; Simulate the SWAB instruction. ; SWAB: MOV #2,R2 ; Get operation size. CALL SGLWRD ; Set up to perform SWAB. SWAB (R1) ; Swap bytes in destination operand. RETURN ; ; Clear one or more condition code bits. ; CLX: BIC R4,SIM.PS ; Clear PS bits. RETURN ; ; Set one or more condition code bits. ; SEX: BIC #^C<17>,R4 ; Mask off garbage. BIS R4,SIM.PS ; Set PS bits. RETURN .PAGE ; ; Simulate the BCC instruction. ; BCC: MTPS SIM.PS ; Get target task condition codes. BCC BRANCH ; Branch if carry clear. RETURN ; ; Simulate the BCS instruction. ; BCS: MTPS SIM.PS ; Get target task condition codes. BCS BRANCH ; Branch if carry set. RETURN ; ; Simulate the BEQ instruction. ; BEQ: MTPS SIM.PS ; Get target task condition codes. BEQ BRANCH ; Branch if Z bit set. RETURN ; ; Simulate the BMI instruction. ; BMI: MTPS SIM.PS ; Get target task condition codes. BMI BRANCH ; Branch if N bit set. RETURN ; ; Simulate the BNE instruction. ; BNE: MTPS SIM.PS ; Get target task condition codes. BNE BRANCH ; Branch if Z bit clear. RETURN ; ; Simulate the BPL instruction. ; BPL: MTPS SIM.PS ; Get target task condition codes. BPL BRANCH ; Branch if N bit clear. RETURN ; ; Simulate a branch. ; BRANCH: MOVB R4,R1 ; Sign extend branch offset. ASL R1 ; Make it a word offset. ADD R1,SIM.PC ; Calculate destination PC. RETURN .PAGE ; ; Simulate the BHI instruction. ; BHI: MTPS SIM.PS ; Get target task condition codes. BHI BRANCH ; Branch if C and Z are both clear. RETURN ; ; Simulate the BLOS instruction. ; BLOS: MTPS SIM.PS ; Get target task condition codes. BLOS BRANCH ; Branch if either C or Z is set. RETURN ; ; Simulate the BGE instruction. ; BGE: MTPS SIM.PS ; Get target task condition codes. BGE BRANCH ; Branch if GE. RETURN ; ; Simulate the BGT instruction. ; BGT: MTPS SIM.PS ; Get target task condition codes. BGT BRANCH ; Branch if GT. RETURN ; ; Simulate the BLE instruction. ; BLE: MTPS SIM.PS ; Get target task condition codes. BLE BRANCH ; Branch if LE. RETURN ; ; Simulate the BLT instruction. ; BLT: MTPS SIM.PS ; Get target task condition codes. BLT BRANCH ; Branch if LT. RETURN ; ; Simulate the SOB instruction. ; SOB: MOV R4,R0 ; Copy opcode word. ASL R0 ; Position register number as a word offset. ASL R0 ASL R0 SWAB R0 BIC #^C<16>,R0 ; Mask off all but register index. BIC #^C<77>,R4 ; Mask opcode to the branch offset. NEG R4 ; Correct offset sign. DEC SIM.R0(R0) ; Should SOB branch? BNE BRANCH ; Yes, take the branch. RETURN .PAGE ; ; Simulate the JSR instruction. ; JSR: MOV R4,-(SP) ; Save opcode word. MOV #2,R2 ; Get operation size. CALL DSTADR ; Get target address. MOV R5,R3 ; Save target address. MOV (SP)+,R4 ; Recover opcode word. ASL R4 ; Make register number a word offset. ASL R4 ASL R4 SWAB R4 BIC #^C<16>,R4 ADD #SIM.R0,R4 ; Point to simulated register. MOV (R4),R1 ; Save linkage register value. SUB #2,SIM.SP ; Make room on simulated stack. MOV SIM.SP,R5 ; Get simulated stack pointer. CALL M$WD5 ; Save linkage register value on stack. MOV SIM.PC,(R4) ; Save return address in linkage register. MOV R3,SIM.PC ; Save target address in PC. RETURN .PAGE ; ; Simulate the ADD instruction. ; ADD: CALL DBLWRD ; Set up everything. ADD R3,(R1) ; Add source operand to destination. RETURN ; ; Simulate the BIC instruction. ; BIC: CALL DBLWRD ; Set up everything. BIC R3,(R1) ; Bit clear source operand to destination. RETURN ; ; Simulate the BIS instruction. ; BIS: CALL DBLWRD ; Set up everything. BIS R3,(R1) ; Bit set source operand to destination. RETURN ; ; Simulate the BIT instruction. ; BIT: CALL DBLWRD ; Set up everything. BIT R3,(R1) ; Bit test source operand to destination. RETURN ; ; Simulate the CMP instruction. ; CMP: CALL DBLWRD ; Set up everything. CMP R3,(R1) ; Compare source operand to destination. RETURN ; ; Simulate the MOV instruction. ; MOV: CALL DBLWRD ; Set up everything. MOV R3,(R1) ; Move source operand to destination. RETURN ; ; Simulate the SUB instruction. ; SUB: CALL DBLWRD ; Set up everything. SUB R3,(R1) ; Subtract source operand from destination. RETURN ; ; Routine to set up for double-operand word operations. ; DBLWRD: CALL SRCWRD ; Get source operand value in R3. SGLWRD: CALL DSTMAP ; Map destination operand. MTPS SIM.PS ; Get target task condition codes. CALL @(SP)+ ; Execute simulated operation. MFPS SIM.PS ; Save resulting condition codes. RETURN .PAGE ; ; Simulate the BICB instruction. ; BICB: CALL DBLBYT ; Set up everything. BICB R3,(R1) ; Bit clear source operand to destination. RETURN ; ; Simulate the BISB instruction. ; BISB: CALL DBLBYT ; Set up everything. BISB R3,(R1) ; Bit set source operand to destination. RETURN ; ; Simulate the BITB instruction. ; BITB: CALL DBLBYT ; Set up everything. BITB R3,(R1) ; Bit test source operand to destination. RETURN ; ; Simulate the CMPB instruction. ; CMPB: CALL DBLBYT ; Set up everything. CMPB R3,(R1) ; Compare source operand to destination. RETURN ; ; Simulate the MOVB instruction. Note code to handle GPR sign extension. ; MOVB: BIT #70,R4 ; Is destination a GPR? BEQ 10$ ; Yes, extend sign into high byte of GPR. CALL DBLBYT ; Set up everything. MOVB R3,(R1) ; Move source operand to destination. RETURN ; Destination is a GPR. 10$: CALL DBLBYT ; Set up everything. MOV R3,(R1) ; Move source operand to destination. RETURN ; ; Routine to set up for double-operand byte operations. ; DBLBYT: CALL SRCBYT ; Get source operand value in R3. CALL DSTMAP ; Map destination operand. MTPS SIM.PS ; Get target task condition codes. CALL @(SP)+ ; Execute simulated operation. MFPS SIM.PS ; Save resulting condition codes. RETURN .PAGE ; ; Simulate the single operand word instructions. ; SINGLW: MOV R4,R0 ; Copy opcode word. SUB #.CLR,R0 ; Subtract lowest opcode in class. ASL R0 ; Position operation bits as a word index. ASL R0 ASL R0 SWAB R0 BIC #^C<36>,R0 ; Mask to operation table index. MOV SGWTBL(R0),-(SP); Push operation routine pointer. MOV #2,R2 ; Set up operation size. CALL DSTMAP ; Map destination operand. MTPS SIM.PS ; Get target task condition codes. JMP @(SP)+ ; Perform the required operation. ; Clear the destination. CLR: CLR (R1) BR SWCSAV ; Complement the destination. COM: COM (R1) BR SWCSAV ; Increment the destination. INC: INC (R1) BR SWCSAV ; Decrement the destination. DEC: DEC (R1) BR SWCSAV ; Negate the destination. NEG: NEG (R1) BR SWCSAV ; Add carry to the destination ADC: ADC (R1) BR SWCSAV ; Subtract carry from the destination. SBC: SBC (R1) BR SWCSAV ; Test the destination. TST: TST (R1) BR SWCSAV ; Rotate the destination right. ROR: ROR (R1) BR SWCSAV ; Rotate the destination left. ROL: ROL (R1) BR SWCSAV ; Shift the destination right arithmetically. ASR: ASR (R1) BR SWCSAV ; Shift the destination left arithmetically. ASL: ASL (R1) ;;; BR SWCSAV SWCSAV: MFPS SIM.PS ; Save resulting condition codes. RETURN .PAGE ; ; Simulate the single operand byte instructions. ; SINGLB: MOV R4,R0 ; Copy opcode word. SUB #.CLRB,R0 ; Subtract lowest opcode in class. ASL R0 ; Position operation bits as a word index. ASL R0 ASL R0 SWAB R0 BIC #^C<36>,R0 ; Mask to operation table index. MOV SGBTBL(R0),-(SP); Push operation routine pointer. MOV #1,R2 ; Set up operation size. CALL DSTMAP ; Map destination operand. MTPS SIM.PS ; Get target task condition codes. JMP @(SP)+ ; Perform the required operation. ; Clear the destination. CLRB: CLRB (R1) BR SWCSAV ; Complement the destination. COMB: COMB (R1) BR SWCSAV ; Increment the destination. INCB: INCB (R1) BR SWCSAV ; Decrement the destination. DECB: DECB (R1) BR SWCSAV ; Negate the destination. NEGB: NEGB (R1) BR SWCSAV ; Add carry to the destination ADCB: ADCB (R1) BR SWCSAV ; Subtract carry from the destination. SBCB: SBCB (R1) BR SWCSAV ; Test the destination. TSTB: TSTB (R1) BR SWCSAV ; Rotate the destination right. RORB: RORB (R1) BR SWCSAV ; Rotate the destination left. ROLB: ROLB (R1) BR SWCSAV ; Shift the destination right arithmetically. ASRB: ASRB (R1) BR SWCSAV ; Shift the destination left arithmetically. ASLB: ASLB (R1) BR SWCSAV SIMEND:: ; End of SIM11 module. .ENDC ; DF I$MTPS .END