   J   SUGGESTED USE:  This is the fact sheet distributed to press and analystsI   needing more information to write about the 21064 microprocessor at the .   time of its announcement, February 25, 1992.         1                     Digital Equipment Corporation '                              Fact Sheet       +  PRODUCT NAME: 21064 150 MHz Microprocessor   E  OVERVIEW:   Digital's 21064 150 MHz microprocessor is the first in a G  family of chips to implement Digital's Alpha architecture. ("Alpha" is H  Digital's internal code name.) The 21064 microprocessor is a .75 micronJ  CMOS-based super-scalar, super-pipelined processor using dual instructionJ  issue and a 150 MHz cycle time (contact Digital for information on fasterE  clock rate implementations). The Alpha architecture is a 64-bit RISC B  architecture designed with particular emphasis on speed, multiple-  instruction issue, and multiple processors.      #  21064 MICROPROCESSOR KEY FEATURES:   2  o Implements the Advanced Alpha RISC Architecture5      - Optimized for high performance implementations       - Multiprocessor support G      - IEEE single and double precision, VAX F_floating and G_floating, (        longword, and quadword data types*      - Cycle counter for code optimization    o Single-chip implementation     o 3.3-volt supply voltage     o High performance "      - Dual-pipelined architectureJ      - 150 MHz cycle time (contact Digital for information on faster clock        rate implementations)F      - Peak instruction execution of 300 million operations per second
        (MIPS)   ;  o Privileged Architecture Library Code (PALcode) supports: 2      - Optimization for multiple operating systems1      - Flexible memory management implementations )      - Multi-instruction atomic sequences   1  o On-chip write buffer with four 32-byte entries   (  o On-chip pipelined floating point unit    o On-chip 8 Kbyte data cache   $  o On-chip 8 Kbyte instruction cache  .  o On-chip demand paged memory management unitJ      - 12-entry I-stream TB with 8 entries for 8 Kbyte pages and 4 entries        for 4 Mbyte pagesJ      - 32-entry D-stream TB with each entry able to map 8 Kbyte, 64 Kbyte,"        512 Kbyte, or 4 Mbyte pages  1  o On-chip parity and ECC generators and checkers    -  o On-chip internal clock generator provides:       - High-speed chip clock:      - Pair of programmable system clocks (CPU/2 to CPU/8)                              -more-     C  o Programmable on-chip performance counters measure CPU and system     performance  G  o Selectable data bus width speed, 64 or 128 bits, 75 MHz to 18.75 MHz   !  o External cache memory support: /      - On-chip external secondary cache control (      - Programmable cache size and speed  %  o Chip and module level test support       Operating Characteristics  D         Power Supply                      Vss 0.0 V, Vdd 3.3 V +/-5%<         Operating Temperature             Tj max = 85 deg. CB         Storage Temperature Range         -55 deg. C to 125 deg. CF         Power Dissipation @Vdd = 3.45V    23 W typical, 27.5 W maximum8                                           Speed = 6.6 ns+         Die Size		          13.9mm x 16.8mm (         Transistor Count		  1.68 million          Package				  431 pin PGA              Alpha Architecture Summary:  F  The 21064 microprocessor implements the Alpha architecture. The Alpha  architecture supports:   !  o A 64-bit virtual address space   0  o Separate integer and floating point registers!     - 32 64-bit integer registers (     - 32 64-bit floating point registers   H  o 32-bit (longword) and 64-bit (quadword) integer along with 32-bit and0    64-bit IEEE and VAX floating-point data types   1  o Privileged Architecture Library Code (PALcode)   J  Instruction Set:  Alpha instructions are all 32 bits in length using fourI  different instruction formats specifying 0, 1, 2, or 3 five-bit register )  fields. Each format uses a 6-bit opcode.   G  Conditional branch instructions test a register for positive/negative, K  zero/nonzero, or even/odd, and perform a PC relative branch. Unconditional K  branch instructions perform either a PC relative or absolute jump using an H  arbitrary 64-bit register value. They can update a destination register  with a return address.   F  Load/Store Instructions can move either 32-bit or 64-bit quantities. J  8-bit and 16-bit load/store operations are supported through an extensive'  set of in-register byte manipulations.   J  Integer Operate Instructions manipulate full 64-bit values, and include aJ  full complement of arithmetic, compare, logical, and shift instructions. H  In addition there are three 32-bit integer operates: add, subtract, and
  multiply.                              -more-     H  The Alpha architecture provides scaled add/subtract for quick subscript=  calculation, 128-bit multiply for division by a constant and K  multiprecision arithmetic, conditional moves for avoiding branches, and an =  extensive set of in-register byte manipulation instructions.   B  Floating-Point Operate Instructions include four complete sets ofC  instructions for IEEE single, IEEE  double, VAX F_floating and VAX H  G_floating arithmetic. In addition to arithmetic instructions there areG  also  instructions for conversions between floating and integer values (  including the VAX D_floating data type.  K  Privileged Architecture Library Code:   PALcode is a privileged library of H  software that atomically performs such functions as the dispatching andD  servicing of interrupts, exceptions, task switching, and additionalH  privileged and unprivileged user instructions as specified by operating(  systems using the CALL_PAL instruction.  K  PALcode is the only method of performing some operations on the hardware.  I  In addition to the entire Alpha instruction set, a set of implementation #  specific instructions is provided.   E  PALcode runs in an environment with privileges enabled, instruction  D  stream mapping disabled, and interrupts disabled.  Disabling memoryG  mapping allows PALcode to support functions such as TB miss routines.  ?  Disabling interrupts allows the  instruction stream to provide 2  multi-instruction sequences as atomic operations.  J  Memory Management:   The Alpha memory management architecture is designedG  to provide a large address space for instructions and data, convenient K  and efficient sharing of instructions and data, independent read and write I  access protection, and flexibility through programmable PALcode support.       Microarchitecture:   G  Digital's 21064 microprocessor consists of four independent functional J  units: the integer execution unit (Ebox), floating point unit (Fbox), theG  load/store or address unit (Abox), and the branch unit. Other sections @  include the central control unit (Ibox) and the I and D cache.   H  The Ebox contains a 64-bit, fully pipelined integer execution data pathH  including: adder, logic box, barrel shifter, byte extract and mask, andI  independent integer multiplier. The Ebox also contains a 32-entry 64-bit   integer register file.   H  The Fbox contains a fully pipelined floating point unit and independentF  divider, supporting both IEEE and VAX floating point data types. IEEED  single-precision and double-precision floating point data types areH  supported. VAX F_floating and G_floating data types are fully supported3  with limited support for the D_floating data type.   K  The Abox contains five major sections: address translation data path, load H  silo, write buffer, Data cache (Dcache), and the external bus interfaceF  unit (BIU). The Abox supports all integer and floating point load andG  store instructions, including address calculation and translation, and   cache control logic.   K  The Ibox performs instruction fetch, resource checks, and dual instruction E  issue to the Ebox, Abox, Fbox, or branch unit. In addition, the Ibox 0  controls pipeline stalls, aborts, and restarts.                            -more-     C  Pipeline Organization: The 21064 microprocessor uses a seven-stage F  pipeline for integer operate and memory reference instructions, and aF  ten-stage pipeline for floating point operate instructions.  The IboxF  maintains state for all pipeline stages to track outstanding register  writes.  C  Cache Organization:  The 21064 microprocessor contains two on-chip H  caches, data cache (D-cache) and instruction cache (I-cache).  The chipH  also supports an external cache. The D-cache contains 8 Kbytes and is aH  write-through, direct-mapped, read-allocate physical cache with 32-byteL  blocks. The I-cache contains 8 Kbytes and is a physical direct-mapped cache  with 32-byte blocks.   G  The 21064 chip supports external cache built from off-the-shelf static H  RAMs. The 21064 chip directly controls the RAMs  using its programmableG  external cache interface, allowing each implementation to make its own 3  external cache speed and configuration trade-offs.   I  The external cache interface supports cache sizes from 0 to 8 Mbytes and F  a range of operating speeds that are sub-multiples of the chip clock.  I  Virtual Address Space:  The virtual address is a 64-bit unsigned integer K  that specifies a byte location within the virtual address space. The 21064 H  microprocessor checks all 64 bits of a virtual address and implements aK  43-bit subset of the address space.  The 21064 supports a physical address   space of 16 Gbytes.          J  PRICING:  Samples (through June 1992) $3375 each. Volume quantities (July(  1992) starting at $1650 (1,000 pieces).    A  AVAILABILITY:  Sample parts available February 1992 for customer G  evaluation. Quantities to support customers' volume ramps available in   July 1992.   &                                  # # #     -  For Further Information Contact our Hotline:    	1-800-DEC-2717 = 	1-800-DEC-2515 (Telecommunications Device for the Deaf  TDD)  	508-568-6868 (local number)     H  Note to Editors:   DEC, the Digital logo, VAX and VMS are trademarks of  Digital Equipment Corporation.   J  OSF/1 is a registered trademark of Open Software Foundation, Inc. UNIX is9  a registered trademark of UNIX System Laboratories, Inc.    