<<< HUMANE::DISK$SCSI:[NOTES$LIBRARY]DIGITAL.NOTE;1 >>> -< The Digital way of working >- ================================================================================ Note 5286.18 Alleged Patent Violations 18 of 18 COVERT::COVERT "John R. Covert" 36 lines 14-MAY-1997 12:36 -------------------------------------------------------------------------------- Extracted from http://www.boston.com/globe/eco/14dectext.htm July 5, 1988, United States Patent No. 4,755,936 titled ``Apparatus And Method For Providing A Cache Memory Unit With A Write Operation Utilizing Two System Clock Cycles'' July 11, 1989, United States Patent No. 4,847,804 titled ``Apparatus And Method For Data Copy Consistency In A Multi-Cache Data Processing Unit'' February 25, 1992, United States Patent No. 5,091,845 titled ``System For Controlling The Storage Of Information In A Cache Memory,'' June 23, 1992, United States Patent No. 5,125,083 titled ``Method And Apparatus For Resolving A Variable Number Of Potential Memory Access Conflicts In A Pipelined Computer System'' September 15, 1992, United States Patent No. 5,148,536 titled ``Pipeline Having An Integral Cache Which Processes Cache Misses And Loads Data In Parallel'' January 12, 1993, United States Patent No. 5.179,673 titled ``Subroutine Return Prediction Mechanism Using Ring Buffer And Comparing Predicated Address With Actual Address To Validate Or Flush The Pipeline'' March 23, 1993, United States Patent No. 5, 197, 132 titled ``Register Mapping System Having A Log Containing Sequential Listing of Registers That Were Changed In Preceding Cycles For Precise Post-Branch Recovery'' February 28, 1995. United States Patent No. 5.394.529 titled `Branch Prediction Unit For High-Performance Processors' July 4, 1995, United Sates No. 5.430.888 titled ``Pipeline Utilizing An Integral Cache For Transferring Data To And From A Register '' October 22, 1996, United states Patent No. 5.568.624 titled ``Byte-Compare Operation For High-Performance Processor''